diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 3a4eb0d3d..8e310d362 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -342,6 +342,9 @@ nvgpu-y += \ common/fifo/channel_gm20b.o \ common/fifo/channel_gv11b.o \ common/fifo/channel_gv100.o \ + common/fifo/engine_status.o \ + common/fifo/engine_status_gm20b.o \ + common/fifo/engine_status_gv100.o \ common/ecc.o \ common/ce2.o \ common/debugger.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 5ab54fe17..cd883378f 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -186,6 +186,9 @@ srcs += common/sim.c \ common/fifo/channel_gm20b.c \ common/fifo/channel_gv11b.c \ common/fifo/channel_gv100.c \ + common/fifo/engine_status.c \ + common/fifo/engine_status_gm20b.c \ + common/fifo/engine_status_gv100.c \ common/mc/mc.c \ common/mc/mc_gm20b.c \ common/mc/mc_gp10b.c \ diff --git a/drivers/gpu/nvgpu/common/fifo/engine_status.c b/drivers/gpu/nvgpu/common/fifo/engine_status.c new file mode 100644 index 000000000..366159e55 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/engine_status.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +bool nvgpu_engine_status_is_ctxsw_switch(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_SWITCH; +} + +bool nvgpu_engine_status_is_ctxsw_load(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_LOAD; +} + +bool nvgpu_engine_status_is_ctxsw_save(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_SAVE; +} + +bool nvgpu_engine_status_is_ctxsw(struct nvgpu_engine_status_info + *engine_status) +{ + return (nvgpu_engine_status_is_ctxsw_switch(engine_status) || + nvgpu_engine_status_is_ctxsw_load(engine_status) || + nvgpu_engine_status_is_ctxsw_save(engine_status)); +} + +bool nvgpu_engine_status_is_ctxsw_invalid(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctxsw_status == NVGPU_CTX_STATUS_INVALID; +} + +bool nvgpu_engine_status_is_ctxsw_valid(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctxsw_status == NVGPU_CTX_STATUS_VALID; +} +bool nvgpu_engine_status_is_ctx_type_tsg(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctx_id_type == ENGINE_STATUS_CTX_ID_TYPE_TSGID; +} +bool nvgpu_engine_status_is_next_ctx_type_tsg(struct nvgpu_engine_status_info + *engine_status) +{ + return engine_status->ctx_next_id_type == + ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID; +} + +void nvgpu_engine_status_get_ctx_id_type(struct nvgpu_engine_status_info + *engine_status, u32 *ctx_id, u32 *ctx_type) +{ + *ctx_id = engine_status->ctx_id; + *ctx_type = engine_status->ctx_id_type; +} + +void nvgpu_engine_status_get_next_ctx_id_type(struct nvgpu_engine_status_info + *engine_status, u32 *ctx_next_id, + u32 *ctx_next_type) +{ + *ctx_next_id = engine_status->ctx_next_id; + *ctx_next_type = engine_status->ctx_next_id_type; +} diff --git a/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.c b/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.c new file mode 100644 index 000000000..4e19d4079 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include + +#include "engine_status_gm20b.h" + +static void populate_invalid_ctxsw_status_info( + struct nvgpu_engine_status_info *status_info) +{ + status_info->ctx_id = ENGINE_STATUS_CTX_ID_INVALID; + status_info->ctx_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID; + status_info->ctx_next_id = + ENGINE_STATUS_CTX_NEXT_ID_INVALID; + status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID; + status_info->ctxsw_status = NVGPU_CTX_STATUS_INVALID; +} + +static void populate_valid_ctxsw_status_info( + struct nvgpu_engine_status_info *status_info) +{ + bool id_type_tsg; + u32 engine_status = status_info->reg_data; + + status_info->ctx_id = + fifo_engine_status_id_v(status_info->reg_data); + id_type_tsg = fifo_engine_status_id_type_v(engine_status) == + fifo_engine_status_id_type_tsgid_v(); + status_info->ctx_id_type = + id_type_tsg ? ENGINE_STATUS_CTX_ID_TYPE_TSGID : + ENGINE_STATUS_CTX_ID_TYPE_CHID; + status_info->ctx_next_id = + ENGINE_STATUS_CTX_NEXT_ID_INVALID; + status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID; + status_info->ctxsw_status = NVGPU_CTX_STATUS_VALID; +} + +static void populate_load_ctxsw_status_info( + struct nvgpu_engine_status_info *status_info) +{ + bool next_id_type_tsg; + u32 engine_status = status_info->reg_data; + + status_info->ctx_id = ENGINE_STATUS_CTX_ID_INVALID; + status_info->ctx_id_type = ENGINE_STATUS_CTX_ID_TYPE_INVALID; + status_info->ctx_next_id = + fifo_engine_status_next_id_v( + status_info->reg_data); + next_id_type_tsg = fifo_engine_status_next_id_type_v(engine_status) == + fifo_engine_status_next_id_type_tsgid_v(); + status_info->ctx_next_id_type = + next_id_type_tsg ? ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID : + ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID; + status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_LOAD; +} + +static void populate_save_ctxsw_status_info( + struct nvgpu_engine_status_info *status_info) +{ + bool id_type_tsg; + u32 engine_status = status_info->reg_data; + + status_info->ctx_id = + fifo_engine_status_id_v(status_info->reg_data); + id_type_tsg = fifo_engine_status_id_type_v(engine_status) == + fifo_engine_status_id_type_tsgid_v(); + status_info->ctx_id_type = + id_type_tsg ? ENGINE_STATUS_CTX_ID_TYPE_TSGID : + ENGINE_STATUS_CTX_ID_TYPE_CHID; + status_info->ctx_next_id = + ENGINE_STATUS_CTX_NEXT_ID_INVALID; + status_info->ctx_next_id_type = ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID; + status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SAVE; +} + +static void populate_switch_ctxsw_status_info( + struct nvgpu_engine_status_info *status_info) +{ + bool id_type_tsg; + bool next_id_type_tsg; + u32 engine_status = status_info->reg_data; + + status_info->ctx_id = + fifo_engine_status_id_v(status_info->reg_data); + id_type_tsg = fifo_engine_status_id_type_v(engine_status) == + fifo_engine_status_id_type_tsgid_v(); + status_info->ctx_id_type = + id_type_tsg ? ENGINE_STATUS_CTX_ID_TYPE_TSGID : + ENGINE_STATUS_CTX_ID_TYPE_CHID; + status_info->ctx_next_id = + fifo_engine_status_next_id_v( + status_info->reg_data); + next_id_type_tsg = fifo_engine_status_next_id_type_v(engine_status) == + fifo_engine_status_next_id_type_tsgid_v(); + status_info->ctx_next_id_type = + next_id_type_tsg ? ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID : + ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID; + status_info->ctxsw_status = NVGPU_CTX_STATUS_CTXSW_SWITCH; +} + +void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id, + struct nvgpu_engine_status_info *status) +{ + u32 engine_reg_data; + u32 ctxsw_state; + + (void) memset(status, 0, sizeof(*status)); + + engine_reg_data = nvgpu_readl(g, fifo_engine_status_r(engine_id)); + + status->reg_data = engine_reg_data; + + /* populate the engine_state enum */ + status->is_busy = fifo_engine_status_engine_v(engine_reg_data) == + fifo_engine_status_engine_busy_v(); + + /* populate the engine_faulted_state enum */ + status->is_faulted = fifo_engine_status_faulted_v(engine_reg_data) == + fifo_engine_status_faulted_true_v(); + + /* populate the ctxsw_in_progress_state */ + status->ctxsw_in_progress = ((engine_reg_data & + fifo_engine_status_ctxsw_in_progress_f()) != 0U); + + /* populate the ctxsw related info */ + ctxsw_state = fifo_engine_status_ctx_status_v(engine_reg_data); + + status->ctxsw_state = ctxsw_state; + + if (ctxsw_state == fifo_engine_status_ctx_status_valid_v()) { + populate_valid_ctxsw_status_info(status); + } else if (ctxsw_state == + fifo_engine_status_ctx_status_ctxsw_load_v()) { + populate_load_ctxsw_status_info(status); + } else if (ctxsw_state == + fifo_engine_status_ctx_status_ctxsw_save_v()) { + populate_save_ctxsw_status_info(status); + } else if (ctxsw_state == + fifo_engine_status_ctx_status_ctxsw_switch_v()) { + populate_switch_ctxsw_status_info(status); + } else { + populate_invalid_ctxsw_status_info(status); + } +} diff --git a/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.h b/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.h new file mode 100644 index 000000000..95ff066e7 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ENGINE_STATUS_GM20B +#define NVGPU_ENGINE_STATUS_GM20B + +#include + +struct gk20a; +struct nvgpu_engine_status_info; + +void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id, + struct nvgpu_engine_status_info *status); + +#endif /* NVGPU_ENGINE_STATUS_GM20B */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.c b/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.c new file mode 100644 index 000000000..397065aae --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include + +#include "engine_status_gm20b.h" +#include "engine_status_gv100.h" + +void read_engine_status_info_gv100(struct gk20a *g, u32 engine_id, + struct nvgpu_engine_status_info *status) +{ + u32 engine_reg_data; + + gm20b_read_engine_status_info(g, engine_id, status); + engine_reg_data = status->reg_data; + /* populate the engine reload status */ + status->in_reload_status = + fifo_engine_status_eng_reload_v(engine_reg_data) != 0U; + + return; +} diff --git a/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.h b/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.h new file mode 100644 index 000000000..db94d2c26 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fifo/engine_status_gv100.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ENGINE_STATUS_GV100 +#define NVGPU_ENGINE_STATUS_GV100 + +#include + +struct gk20a; +struct nvgpu_engine_status_info; + +void read_engine_status_info_gv100(struct gk20a *g, u32 engine_id, + struct nvgpu_engine_status_info *status); + +#endif \ No newline at end of file diff --git a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h new file mode 100644 index 000000000..ff92bd060 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ENGINE_STATUS_H +#define NVGPU_ENGINE_STATUS_H + +#define ENGINE_STATUS_CTX_ID_TYPE_CHID 0U +#define ENGINE_STATUS_CTX_ID_TYPE_TSGID 1U +#define ENGINE_STATUS_CTX_ID_TYPE_INVALID (~U32(0U)) + +#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID ENGINE_STATUS_CTX_ID_TYPE_CHID +#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID ENGINE_STATUS_CTX_ID_TYPE_TSGID +#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID ENGINE_STATUS_CTX_ID_TYPE_INVALID + +#define ENGINE_STATUS_CTX_ID_INVALID (~U32(0U)) +#define ENGINE_STATUS_CTX_NEXT_ID_INVALID ENGINE_STATUS_CTX_ID_INVALID + +enum nvgpu_engine_status_ctx_status { + NVGPU_CTX_STATUS_INVALID, + NVGPU_CTX_STATUS_VALID, + NVGPU_CTX_STATUS_CTXSW_LOAD, + NVGPU_CTX_STATUS_CTXSW_SAVE, + NVGPU_CTX_STATUS_CTXSW_SWITCH, +}; + +struct nvgpu_engine_status_info { + u32 reg_data; + u32 ctx_id; + u32 ctxsw_state; + u32 ctx_id_type; + u32 ctx_next_id; + u32 ctx_next_id_type; + + bool is_faulted; + bool is_busy; + bool ctxsw_in_progress; + bool in_reload_status; + enum nvgpu_engine_status_ctx_status ctxsw_status; +}; + +bool nvgpu_engine_status_is_ctxsw_switch(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctxsw_load(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctxsw_save(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctxsw(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctxsw_invalid(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctxsw_valid(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_ctx_type_tsg(struct nvgpu_engine_status_info + *engine_status); +bool nvgpu_engine_status_is_next_ctx_type_tsg(struct nvgpu_engine_status_info + *engine_status); +void nvgpu_engine_status_get_ctx_id_type(struct nvgpu_engine_status_info + *engine_status, u32 *ctx_id, u32 *ctx_type); +void nvgpu_engine_status_get_next_ctx_id_type(struct nvgpu_engine_status_info + *engine_status, u32 *ctx_next_id, + u32 *ctx_next_type); + +#endif /* NVGPU_ENGINE_STATUS_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index c13e5dfaf..d8881a46f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -64,6 +64,7 @@ struct nvgpu_sgl; struct nvgpu_device_info; struct nvgpu_gr_subctx; struct nvgpu_channel_hw_state; +struct nvgpu_engine_status_info; #include #include @@ -914,6 +915,10 @@ struct gpu_ops { void (*reset_faulted)(struct gk20a *g, struct channel_gk20a *ch, bool eng, bool pbdma); } channel; + struct { + void (*read_engine_status_info) (struct gk20a *g, + u32 engine_id, struct nvgpu_engine_status_info *status); + } engine_status; struct pmu_v { u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu,