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gpu: nvgpu: improve doxygen for qnx.os_utils and common.io units

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Fix the os_utils DVR issues found as part of 5.2 SWUD Lite units design
verification. Patch improve doxygen for common.io and firmware unit.

Jira NVGPU-6618

Change-Id: Ia0e2cfb3c222de8e080337f1c8957907e321d11d
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515455
(cherry picked from commit 07a15ce3e096dd9a7dff1b4b13c2eed4d604fbb9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515511
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Prateek sethi
2021-04-15 16:38:50 +05:30
committed by mobile promotions
parent 49ad421542
commit e60d373fab
2 changed files with 17 additions and 11 deletions
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6
drivers/gpu/nvgpu/include/nvgpu/firmware.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -55,9 +55,9 @@ struct nvgpu_firmware {
* (These flags are inconsequential in case of rmos.)
*
* - nvgpu_request_firmware() will load firmware from:
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* <system firmware load path>/<GPU name>/<fw_name>
* If that fails and NO_SOC is not enabled, it'll try next from:
* <system firmware load path>/<SOC name>/<fw_name>
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* - It'll allocate a nvgpu_firmware structure and initializes it and returns
* it to caller.
* - nvgpu_firmware will have pointer to fw data which will be filled with the

22
drivers/gpu/nvgpu/include/nvgpu/io.h
View File

@@ -88,7 +88,9 @@ struct gk20a;
* @param v [in] Value to write at the offset.
*
* Write a 32-bit value to register offset in GPU IO space with an
* ordering constraint on memory operations.
* ordering constraint on memory operations. API supports write from offset 0 to
* TEGRA_GK20A_BAR0_SIZE but check for this range is not imposed as this is
* called frequently.
*
* @return None.
*/
@@ -102,8 +104,8 @@ void nvgpu_writel(struct gk20a *g, u32 r, u32 v);
* @param r [in] Register offset in GPU IO space.
* @param v [in] Value to write at the offset.
*
* Write a 32-bit value to register offset in GPU IO space without
* an ordering constraint on memory operations.
* Write a 32-bit value to register offset in GPU IO space without an ordering
* constraint on memory operations. This function is implemented by the OS layer.
*
* @return None.
*/
@@ -117,9 +119,11 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v);
* @param r [in] Register offset in GPU IO space.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
*
* Read a 32-bit value from register offset in GPU IO space. If all
* the bits are set in the value read then check for gpu state validity.
* Refer #nvgpu_check_gpu_state() for gpu state validity check.
* Read a 32-bit value from register offset in GPU IO space. If all the bits are
* set in the value read then check for gpu state validity. Refer
* #nvgpu_check_gpu_state() for gpu state validity check. API supports read
* from offset 0 to TEGRA_GK20A_BAR0_SIZE but check for this range is not imposed
* as this is called frequently.
*
* @return Value at the given register offset in GPU IO space.
*/
@@ -132,8 +136,10 @@ u32 nvgpu_readl(struct gk20a *g, u32 r);
* @param r [in] Register offset in GPU IO space.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
*
* Read a 32-bit to register offset from a GPU IO space. nvgpu_readl() is
* called from this function. This function is implemented by the OS layer.
* Read a 32-bit value from register offset in GPU IO space. If all the bits are
* set in the value read then check for gpu state validity. API supports read
* from offset 0 to TEGRA_GK20A_BAR0_SIZE but check for this range is not imposed
* as this is called frequently.
*
* @return Value at the given register offset in GPU IO space.
*/