From e61452ab5c8de5dfc87529ca8d00b6a3bdbd1588 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Fri, 3 May 2019 11:18:41 -0700 Subject: [PATCH] gpu: nvgpu: tsg MISRA fixes for Rule 10.8 roundup() violates MISRA Rule 10.8 when using operands of different sizes. Use u32 operands. Jira NVGPU-3259 Change-Id: Iff8983347cfef0d63fc6a51c2df1b2798eba48f9 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2111434 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Philip Elcan GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c index 64c247278..5d7c05b0f 100644 --- a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c @@ -101,13 +101,14 @@ void gv11b_tsg_bind_channel_eng_method_buffers(struct tsg_gk20a *tsg, g->ops.ramin.set_eng_method_buffer(g, &ch->inst_block, gpu_va); } -static unsigned int gv11b_tsg_get_eng_method_buffer_size(struct gk20a *g) +static u32 gv11b_tsg_get_eng_method_buffer_size(struct gk20a *g) { - unsigned int buffer_size; + u32 buffer_size; + u32 page_size = U32(PAGE_SIZE); buffer_size = ((9U + 1U + 3U) * g->ops.ce.get_num_pce(g)) + 2U; buffer_size = (27U * 5U * buffer_size); - buffer_size = roundup(buffer_size, PAGE_SIZE); + buffer_size = roundup(buffer_size, page_size); nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size); return buffer_size;