diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c index 390cf73c3..a64b81842 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c @@ -723,7 +723,7 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) switch (flcn->flcn_id) { case FALCON_ID_PMU: - flcn->flcn_base = FALCON_PWR_BASE; + flcn->flcn_base = g->ops.pmu.falcon_base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = true; break; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c index 7a90e7d3e..fe8e4193f 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gp106.c @@ -61,7 +61,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn) switch (flcn->flcn_id) { case FALCON_ID_PMU: - flcn->flcn_base = FALCON_PWR_BASE; + flcn->flcn_base = g->ops.pmu.falcon_base_addr(); flcn->is_falcon_supported = true; flcn->is_interrupt_enabled = true; break; diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c index 90c1d901e..f22295e76 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c @@ -878,3 +878,8 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, pg_stat_data->avg_entry_latency_us = stats.pg_avg_entry_time_us; pg_stat_data->avg_exit_latency_us = stats.pg_avg_exit_time_us; } + +u32 gk20a_pmu_falcon_base_addr(void) +{ + return pwr_falcon_irqsset_r(); +} diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h index 37a52762c..3a6cd3366 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h @@ -74,6 +74,7 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, void *param, u32 handle, u32 status); void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data); +u32 gk20a_pmu_falcon_base_addr(void); bool gk20a_pmu_is_engine_in_reset(struct gk20a *g); int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset); u32 gk20a_pmu_get_irqdest(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c index 5469f7609..536e88e16 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c @@ -363,3 +363,8 @@ void gp106_pmu_setup_apertures(struct gk20a *g) pwr_pmu_new_instblk_target_sys_coh_f(), pwr_pmu_new_instblk_target_fb_f())); } + +u32 gp106_pmu_falcon_base_addr(void) +{ + return pwr_falcon_irqsset_r(); +} diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h index c9392d7b6..76022eda9 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.h @@ -43,5 +43,6 @@ bool gp106_pmu_is_engine_in_reset(struct gk20a *g); int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset); void gp106_update_lspmu_cmdline_args(struct gk20a *g); void gp106_pmu_setup_apertures(struct gk20a *g); +u32 gp106_pmu_falcon_base_addr(void); #endif /* NVGPU_PMU_GP106_H */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 5182b4aee..2447eee0c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -588,6 +588,7 @@ static const struct gpu_ops gm20b_ops = { .elcg_init_idle_filters = gm20b_elcg_init_idle_filters, }, .pmu = { + .falcon_base_addr = gk20a_pmu_falcon_base_addr, .pmu_setup_elpg = gm20b_pmu_setup_elpg, .pmu_get_queue_head = pwr_pmu_queue_head_r, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 227f63257..e09d6f745 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -706,6 +706,7 @@ static const struct gpu_ops gp106_ops = { .configure_therm_alert = gp106_configure_therm_alert, }, .pmu = { + .falcon_base_addr = gp106_pmu_falcon_base_addr, .init_wpr_region = gm20b_pmu_init_acr, .load_lsfalcon_ucode = gp106_load_falcon_ucode, .is_lazy_bootstrap = gp106_is_lazy_bootstrap, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2f61ccba0..3cad32af0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -664,6 +664,7 @@ static const struct gpu_ops gp10b_ops = { .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, .pmu = { + .falcon_base_addr = gk20a_pmu_falcon_base_addr, .pmu_setup_elpg = gp10b_pmu_setup_elpg, .pmu_get_queue_head = pwr_pmu_queue_head_r, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ba833a1ad..8807aa5aa 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -842,6 +842,7 @@ static const struct gpu_ops gv100_ops = { .configure_therm_alert = gp106_configure_therm_alert, }, .pmu = { + .falcon_base_addr = gp106_pmu_falcon_base_addr, .init_wpr_region = gv100_pmu_init_acr, .load_lsfalcon_ucode = gv100_load_falcon_ucode, .is_lazy_bootstrap = gp106_is_lazy_bootstrap, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index c85e75831..daf266da0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -793,6 +793,7 @@ static const struct gpu_ops gv11b_ops = { .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { + .falcon_base_addr = gk20a_pmu_falcon_base_addr, .pmu_setup_elpg = gv11b_pmu_setup_elpg, .pmu_get_queue_head = pwr_pmu_queue_head_r, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 0ecce2bb3..54a2afc16 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -42,7 +42,6 @@ /* * Falcon Base address Defines */ -#define FALCON_PWR_BASE 0x0010a000U #define FALCON_SEC_BASE 0x00087000U #define FALCON_FECS_BASE 0x00409000U #define FALCON_GPCCS_BASE 0x0041a000U diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 7b70cb307..252cb11eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1128,6 +1128,7 @@ struct gpu_ops { } therm; struct { bool (*is_pmu_supported)(struct gk20a *g); + u32 (*falcon_base_addr)(void); int (*prepare_ucode)(struct gk20a *g); int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); int (*pmu_nsbootstrap)(struct nvgpu_pmu *pmu); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 0fee16162..762b2c714 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -871,6 +871,7 @@ static const struct gpu_ops tu104_ops = { gp106_get_internal_sensor_limits, }, .pmu = { + .falcon_base_addr = gp106_pmu_falcon_base_addr, .init_wpr_region = NULL, .load_lsfalcon_ucode = gv100_load_falcon_ucode, .is_lazy_bootstrap = gp106_is_lazy_bootstrap,