diff --git a/drivers/gpu/nvgpu/clk/clk_fll.h b/drivers/gpu/nvgpu/clk/clk_fll.h index 5f7fea4ee..f3412d6df 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/clk/clk_fll.h @@ -71,11 +71,11 @@ u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain); u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain); #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \ - (pclk->avfs_fllobjs.lut_num_entries) + ((pclk)->avfs_fllobjs.lut_num_entries) #define CLK_FLL_LUT_MIN_VOLTAGE_UV(pclk) \ - (pclk->avfs_fllobjs.lut_min_voltage_uv) + ((pclk)->avfs_fllobjs.lut_min_voltage_uv) #define CLK_FLL_LUT_STEP_SIZE_UV(pclk) \ - (pclk->avfs_fllobjs.lut_step_size_uv) + ((pclk)->avfs_fllobjs.lut_step_size_uv) #endif /* NVGPU_CLK_FLL_H */ diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c index cc65c68cd..669a73419 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu.c @@ -38,7 +38,7 @@ #define __gmmu_dbg(g, attrs, fmt, args...) \ do { \ - if (attrs->debug) { \ + if ((attrs)->debug) { \ nvgpu_info(g, fmt, ##args); \ } else { \ nvgpu_log(g, gpu_dbg_map, fmt, ##args); \ @@ -47,7 +47,7 @@ #define __gmmu_dbg_v(g, attrs, fmt, args...) \ do { \ - if (attrs->debug) { \ + if ((attrs)->debug) { \ nvgpu_info(g, fmt, ##args); \ } else { \ nvgpu_log(g, gpu_dbg_map_v, fmt, ##args); \ diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index 08297c1ab..2e00b5089 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c @@ -37,15 +37,15 @@ #define __lock_sema_sea(s) \ do { \ - gpu_sema_verbose_dbg(s->gk20a, "Acquiring sema lock..."); \ - nvgpu_mutex_acquire(&s->sea_lock); \ - gpu_sema_verbose_dbg(s->gk20a, "Sema lock aquried!"); \ + gpu_sema_verbose_dbg((s)->gk20a, "Acquiring sema lock..."); \ + nvgpu_mutex_acquire(&(s)->sea_lock); \ + gpu_sema_verbose_dbg((s)->gk20a, "Sema lock aquried!"); \ } while (0) #define __unlock_sema_sea(s) \ do { \ - nvgpu_mutex_release(&s->sea_lock); \ - gpu_sema_verbose_dbg(s->gk20a, "Released sema lock"); \ + nvgpu_mutex_release(&(s)->sea_lock); \ + gpu_sema_verbose_dbg((s)->gk20a, "Released sema lock"); \ } while (0) /* diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c index 4d9f785c3..93c4f440d 100644 --- a/drivers/gpu/nvgpu/common/vbios/bios.c +++ b/drivers/gpu/nvgpu/common/vbios/bios.c @@ -160,7 +160,7 @@ struct falcon_ucode_table_entry_v1 { #define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1U #define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr) \ - ((hdr.v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \ + (((hdr).v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \ FALCON_UCODE_FLAGS_VERSION_AVAILABLE) /* @@ -169,10 +169,10 @@ struct falcon_ucode_table_entry_v1 { */ #define FALCON_UCODE_GET_VERSION(hdr) \ - ((hdr.v2.v_desc >> 8) & 0xffU) + (((hdr).v2.v_desc >> 8) & 0xffU) #define FALCON_UCODE_GET_DESC_SIZE(hdr) \ - ((hdr.v2.v_desc >> 16) & 0xffffU) + (((hdr).v2.v_desc >> 16) & 0xffffU) struct falcon_ucode_desc_v1 { union { diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index dc51fb708..7dd0c91c9 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -48,7 +48,7 @@ */ #define MAX_CE_SHIFT 31 /* 4Gpixels -1 */ #define MAX_CE_MASK ((u32) (~(~0U << MAX_CE_SHIFT))) -#define MAX_CE_ALIGN(a) (a & MAX_CE_MASK) +#define MAX_CE_ALIGN(a) ((a) & MAX_CE_MASK) static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index c4ce49af4..222f442fd 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -57,7 +57,7 @@ #define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2 #define PATCH_CTX_SLOTS_PER_PAGE \ (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) -#define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) +#define PATCH_CTX_ENTRIES_FROM_SIZE(size) ((size)/sizeof(u32)) #define NVGPU_PREEMPTION_MODE_GRAPHICS_WFI (1 << 0) #define NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP (1 << 1) @@ -593,15 +593,15 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); #define gr_gk20a_elpg_protected_call(g, func) \ ({ \ int err = 0; \ - if ((g->support_pmu) && (g->elpg_enabled)) {\ + if (((g)->support_pmu) && ((g)->elpg_enabled)) {\ err = nvgpu_pmu_disable_elpg(g); \ if (err != 0) {\ nvgpu_pmu_enable_elpg(g); \ } \ } \ if (err == 0) { \ - err = func; \ - if ((g->support_pmu) && (g->elpg_enabled)) {\ + err = (func); \ + if (((g)->support_pmu) && ((g)->elpg_enabled)) {\ nvgpu_pmu_enable_elpg(g); \ } \ } \ diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c index a97b9efb5..e021655cb 100644 --- a/drivers/gpu/nvgpu/gv100/bios_gv100.c +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c @@ -35,7 +35,7 @@ #define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ #define SCRATCH_PREOS_PROGRESS 6 -#define PREOS_PROGRESS_MASK(r) ((r >> 12) & 0xf) +#define PREOS_PROGRESS_MASK(r) (((r) >> 12) & 0xf) #define PREOS_PROGRESS_NOT_STARTED 0 #define PREOS_PROGRESS_STARTED 1 #define PREOS_PROGRESS_EXIT 2 @@ -43,11 +43,11 @@ #define PREOS_PROGRESS_ABORTED 6 #define SCRATCH_PMU_EXIT_AND_HALT 1 -#define PMU_EXIT_AND_HALT_SET(r, v) ((r & ~0x200UL) | v) +#define PMU_EXIT_AND_HALT_SET(r, v) (((r) & ~0x200UL) | (v)) #define PMU_EXIT_AND_HALT_YES (0x1UL << 9) #define SCRATCH_PRE_OS_RELOAD 1 -#define PRE_OS_RELOAD_SET(r, v) ((r & ~0x100UL) | v) +#define PRE_OS_RELOAD_SET(r, v) (((r) & ~0x100UL) | (v)) #define PRE_OS_RELOAD_YES (0x1UL << 8) diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h index 57b43c8aa..6164f90d2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h @@ -68,20 +68,20 @@ struct flcn_ucode_img_v1 { */ #define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) #define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2)) #define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2) + 1) #define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((N)*2) - 1) #define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) #define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2)) #define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2) + 1) #define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((N)*2) - 1) #define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) diff --git a/drivers/gpu/nvgpu/include/nvgpu/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/barrier.h index f0b6b2b1a..057faff98 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/barrier.h +++ b/drivers/gpu/nvgpu/include/nvgpu/barrier.h @@ -47,7 +47,7 @@ #define nvgpu_read_barrier_depends() __nvgpu_read_barrier_depends() #define nvgpu_smp_read_barrier_depends() __nvgpu_smp_read_barrier_depends() -#define NV_ACCESS_ONCE(x) __NV_ACCESS_ONCE(x) +#define NV_ACCESS_ONCE(x) __NV_ACCESS_ONCE((x)) /* * Sometimes we want to prevent speculation. diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 4b7d08a18..de8916781 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -529,9 +529,9 @@ struct vfield_header { #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10U -#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1FU) -#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0U) >> 5U) -#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00U) >> 10U) +#define VFIELD_BIT_START(ventry) ((ventry).strap_desc & 0x1FU) +#define VFIELD_BIT_STOP(ventry) (((ventry).strap_desc & 0x3E0U) >> 5U) +#define VFIELD_BIT_REG(ventry) (((ventry).strap_desc & 0x3C00U) >> 10U) #define VFIELD_ENTRY_SIZE 3U diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h index 0ae5bfa89..90324dc35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h @@ -263,17 +263,19 @@ struct boardobjgrp { * If @ref _pmask is provided only objects specified by the mask are traversed. */ #define BOARDOBJGRP_ITERATOR(_pgrp, _ptype, _pobj, _index, _pmask) \ - for (_index = CTRL_BOARDOBJ_IDX_INVALID, \ - _pobj = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), &_index, (_pmask));\ - _pobj != NULL; \ - _pobj = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), &_index, (_pmask))) + for ((_index) = CTRL_BOARDOBJ_IDX_INVALID, \ + (_pobj) = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), \ + &(_index), (_pmask)); \ + (_pobj) != NULL; \ + (_pobj) = (_ptype)boardobjgrpobjgetnextsafe((_pgrp), \ + &(_index), (_pmask))) #define BOARDOBJGRP_FOR_EACH(_pgrp, _ptype, _pobj, _index) \ BOARDOBJGRP_ITERATOR(_pgrp, _ptype, _pobj, _index, NULL) #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \ { \ u##mask_width lcl_msk = (u##mask_width)(mask); \ - for (index = 0; lcl_msk != 0U; index++, lcl_msk >>= 1U) { \ + for ((index) = 0; lcl_msk != 0U; (index)++, lcl_msk >>= 1U) { \ if (((u##mask_width)((u64)1) & lcl_msk) == 0U) { \ continue; \ } @@ -323,7 +325,7 @@ do { \ #define BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, eng, ENG, \ class, CLASS) \ - g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \ + (g)->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \ g, /* pgpu */ \ pboardobjgrp, /* pboardobjgrp */ \ &((pboardobjgrp)->pmu.set), /* pcmd */ \ @@ -337,7 +339,7 @@ do { \ #define BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, pboardobjgrp, \ eng, ENG, class, CLASS) \ - g->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \ + (g)->ops.pmu_ver.boardobj.boardobjgrp_pmucmd_construct_impl( \ g, /* pGpu */ \ pboardobjgrp, /* pBoardObjGrp */ \ &((pboardobjgrp)->pmu.getstatus), /* pCmd */ \ @@ -379,10 +381,10 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); #define HIGHESTBITIDX_32(n32) \ { \ u32 count = 0U; \ - while (n32 >>= 1U) { \ + while ((n32) >>= 1U) { \ count++; \ } \ - n32 = count; \ + (n32) = count; \ } #define LOWESTBIT(x) ((x) & (((x)-1U) ^ (x))) @@ -403,9 +405,9 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); #define NUMSETBITS_32(n32) \ { \ - n32 = n32 - ((n32 >> 1U) & 0x55555555U); \ - n32 = (n32 & 0x33333333U) + ((n32 >> 2U) & 0x33333333U); \ - n32 = (((n32 + (n32 >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U; \ + (n32) = (n32) - (((n32) >> 1U) & 0x55555555U); \ + (n32) = ((n32) & 0x33333333U) + (((n32) >> 2U) & 0x33333333U); \ + (n32) = ((((n32) + ((n32) >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U;\ } #define IDX_32(n32) \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 4fc97ee85..dd422fb6c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -86,10 +86,10 @@ #define FALCON_MAILBOX_COUNT 0x02 #define FALCON_BLOCK_SIZE 0x100U -#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8) +#define GET_IMEM_TAG(IMEM_ADDR) ((IMEM_ADDR) >> 8) #define GET_NEXT_BLOCK(ADDR) \ - ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \ + (((((ADDR) + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \ / FALCON_BLOCK_SIZE) << 8) /* diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index a70015f8e..08dcf8a64 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h @@ -330,7 +330,7 @@ int __nvgpu_set_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte); */ #define pte_dbg(g, attrs, fmt, args...) \ do { \ - if ((attrs != NULL) && (attrs->debug)) \ + if (((attrs) != NULL) && ((attrs)->debug)) \ nvgpu_info(g, fmt, ##args); \ else \ nvgpu_log(g, gpu_dbg_pte, fmt, ##args); \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/list.h b/drivers/gpu/nvgpu/include/nvgpu/list.h index 160803534..ab7f12a7c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/list.h +++ b/drivers/gpu/nvgpu/include/nvgpu/list.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -91,14 +91,14 @@ static inline void nvgpu_list_replace_init(struct nvgpu_list_node *old_node, str nvgpu_list_entry((ptr)->prev, type, member) #define nvgpu_list_for_each_entry(pos, head, type, member) \ - for (pos = nvgpu_list_first_entry(head, type, member); \ - &pos->member != (head); \ - pos = nvgpu_list_next_entry(pos, type, member)) + for ((pos) = nvgpu_list_first_entry(head, type, member); \ + &(pos)->member != (head); \ + (pos) = nvgpu_list_next_entry(pos, type, member)) #define nvgpu_list_for_each_entry_safe(pos, n, head, type, member) \ - for (pos = nvgpu_list_first_entry(head, type, member), \ - n = nvgpu_list_next_entry(pos, type, member); \ - &pos->member != (head); \ - pos = n, n = nvgpu_list_next_entry(n, type, member)) + for ((pos) = nvgpu_list_first_entry(head, type, member), \ + (n) = nvgpu_list_next_entry(pos, type, member); \ + &(pos)->member != (head); \ + (pos) = (n), (n) = nvgpu_list_next_entry(n, type, member)) #endif /* NVGPU_LIST_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h index 70a167620..f4911e0b2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/log.h +++ b/drivers/gpu/nvgpu/include/nvgpu/log.h @@ -107,7 +107,7 @@ int nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask); * Print a message if the log_mask matches the enabled debugging. */ #define nvgpu_log(g, log_mask, fmt, arg...) \ - __nvgpu_log_dbg(g, (u32)log_mask, __func__, __LINE__, fmt, ##arg) + __nvgpu_log_dbg(g, (u32)(log_mask), __func__, __LINE__, fmt, ##arg) /** * nvgpu_err - Print an error diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h index 469754b12..95366ff71 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h +++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h @@ -31,7 +31,7 @@ #define BITS_PER_BYTE 8UL #define BITS_PER_LONG (__SIZEOF_LONG__ * BITS_PER_BYTE) #define BITS_TO_LONGS(bits) \ - (bits + (BITS_PER_LONG - 1) / BITS_PER_LONG) + ((bits) + (BITS_PER_LONG - 1) / BITS_PER_LONG) /* * Deprecated; use the explicit BITxx() macros instead. diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h index 12078b94d..fc40f5ba9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h +++ b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -64,11 +64,11 @@ typedef signed long long s64; #define min(a, b) \ ({ \ - (a) < (b) ? a : b; \ + (a) < (b) ? (a) : (b); \ }) #define max(a, b) \ ({ \ - (a) > (b) ? a : b; \ + (a) > (b) ? (a) : (b); \ }) #define min3(a, b, c) min(min(a, b), c) @@ -183,7 +183,7 @@ static inline unsigned long __hweight64(uint64_t x) #define WRITE_ONCE(p, v) \ ({ \ volatile typeof(p) *__p__ = &(p); \ - *__p__ = v; \ + *__p__ = (v); \ }) #define container_of(ptr, type, member) ({ \