From e6a8e63bb651042e30fb7f5d44eb4993c090de41 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 May 2019 11:29:51 -0700 Subject: [PATCH] gpu: nvgpu: channel MISRA fix for Rule 10.1 JIRA NVGPU-3388 Change-Id: I11b287239a36eaab5582428eb0d209520d0f286a Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2114871 Reviewed-by: svc-mobile-coverity Reviewed-by: Philip Elcan Reviewed-by: Thomas Fleury Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/channel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 7635b778a..e06722b38 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -1027,7 +1027,7 @@ bool channel_gk20a_joblist_is_empty(struct nvgpu_channel *c) if (channel_gk20a_is_prealloc_enabled(c)) { u32 get = c->joblist.pre_alloc.get; u32 put = c->joblist.pre_alloc.put; - return !(CIRC_CNT(put, get, c->joblist.pre_alloc.length)); + return (CIRC_CNT(put, get, c->joblist.pre_alloc.length) == 0U); } return nvgpu_list_empty(&c->joblist.dynamic.jobs);