From e7c9a5309c37d3e824f81c41e736ad1334633932 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Wed, 27 Feb 2019 10:31:38 +0530 Subject: [PATCH] gpu: nvgpu: Fix MISRA 2.1 violation in nvlink MISRA rule 2.1 does not allow having unreachable code. Fix such violation in nvlink by removing the unreachable statement. JIRA NVGPU-1921 Change-Id: I49e55b7a37c81622fef8d90d5f03a0529754c0de Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/2029029 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/common/nvlink/nvlink_gv100.c | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c index 43d677527..e58c0a814 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c @@ -1706,23 +1706,22 @@ enum nvgpu_nvlink_sublink_mode gv100_nvlink_link_get_sublink_mode( return nvgpu_nvlink_sublink_tx_off; } return nvgpu_nvlink_sublink_tx__last; - } else { - state = g->ops.nvlink.get_rx_sublink_state(g, link_id); - if (state == nvl_sl1_slsm_status_rx_primary_state_hs_v()) { - return nvgpu_nvlink_sublink_rx_hs; - } - if (state == nvl_sl1_slsm_status_rx_primary_state_eighth_v()) { - return nvgpu_nvlink_sublink_rx_single_lane; - } - if (state == nvl_sl1_slsm_status_rx_primary_state_safe_v()) { - return nvgpu_nvlink_sublink_rx_safe; - } - if (state == nvl_sl1_slsm_status_rx_primary_state_off_v()) { - return nvgpu_nvlink_sublink_rx_off; - } - return nvgpu_nvlink_sublink_rx__last; } - return nvgpu_nvlink_sublink_tx__last; + + state = g->ops.nvlink.get_rx_sublink_state(g, link_id); + if (state == nvl_sl1_slsm_status_rx_primary_state_hs_v()) { + return nvgpu_nvlink_sublink_rx_hs; + } + if (state == nvl_sl1_slsm_status_rx_primary_state_eighth_v()) { + return nvgpu_nvlink_sublink_rx_single_lane; + } + if (state == nvl_sl1_slsm_status_rx_primary_state_safe_v()) { + return nvgpu_nvlink_sublink_rx_safe; + } + if (state == nvl_sl1_slsm_status_rx_primary_state_off_v()) { + return nvgpu_nvlink_sublink_rx_off; + } + return nvgpu_nvlink_sublink_rx__last; } /*