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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
gpu: nvgpu: add control-fifo queues
Added implementation for following IOCTLs NVGPU_NVS_CTRL_FIFO_CREATE_QUEUE NVGPU_NVS_CTRL_FIFO_RELEASE_QUEUE The above ioctls are supported only for users with R/W permissions. 1) NVGPU_NVS_CTRL_FIFO_CREATE_QUEUE constructs a memory region via the nvgpu_dma_alloc_sys() API and creates the corresponding GPU and kernel mappings. Upon successful creation, KMD exports this buffer to the userspace via a dmabuf fd that the UMD can use to mmap it into its process address space. 2) Added plumbing to store VMA's corresponding to different users for event queue in future. 3) Added necessary validation checks for the IOCTLs 4) NVGPU_NVS_CTRL_FIFO_RELEASE_QUEUE is used to clear the queues. 5) Using a global queue lock to protect access to the queues. This could be modified to be more fine-grained in future when there is more clarity on GSP's implementation and access of queues. 6) Added plumbing to enable user subscription to queues. NVGPU_NVS_CTRL_FIFO_RELEASE_QUEUE is used to unsubscribe the user from the queue. Once, the last user is deleted, all the queues will be cleared. User must ensure that any mappings are removed before calling release queue. 7) Set the default queue_size for event queues to PAGE_SIZE. This can be modified later. For event queues, UMD shall fetch the queue_size. Jira NVGPU-8129 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Change-Id: I31633174e960ec6feb77caede9d143b3b3c145d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2723198 Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
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ee8403175d
commit
e7f9de6567
@@ -15,6 +15,7 @@
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#include <linux/fs.h>
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#include <linux/file.h>
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#include <linux/uaccess.h>
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#include <linux/dma-buf.h>
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#include <uapi/linux/nvgpu-nvs.h>
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@@ -28,6 +29,7 @@
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#include <nvs/domain.h>
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#include "ioctl.h"
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#include "dmabuf_nvs.h"
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/*
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* OS-specific layer to hold device node mapping for a domain.
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@@ -665,6 +667,9 @@ int nvgpu_nvs_ctrl_fifo_ops_release(struct inode *inode, struct file *filp)
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}
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nvgpu_nvs_ctrl_fifo_remove_user(g->sched_ctrl_fifo, &linux_user->user);
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if (!nvgpu_nvs_ctrl_fifo_is_busy(g->sched_ctrl_fifo)) {
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nvgpu_nvs_ctrl_fifo_erase_all_queues(g);
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}
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filp->private_data = NULL;
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@@ -675,3 +680,352 @@ int nvgpu_nvs_ctrl_fifo_ops_release(struct inode *inode, struct file *filp)
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}
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extern const struct file_operations nvgpu_nvs_ctrl_fifo_ops;
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static int nvgpu_nvs_ctrl_fifo_create_queue_verify_flags(struct gk20a *g,
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struct nvs_domain_ctrl_fifo_user *user,
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struct nvgpu_nvs_ctrl_fifo_ioctl_create_queue_args *args)
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{
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int err = 0;
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if (args->reserve0 != 0) {
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return -EINVAL;
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}
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if (args->dmabuf_fd != 0) {
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return -EINVAL;
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}
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if (args->queue_size != 0) {
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return -EINVAL;
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}
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if (args->access_type == NVS_CTRL_FIFO_QUEUE_ACCESS_TYPE_EXCLUSIVE) {
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if (args->queue_num == 0)
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return -EINVAL;
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if (args->direction == 0)
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return -EINVAL;
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if (!nvgpu_nvs_ctrl_fifo_is_exclusive_user(g->sched_ctrl_fifo, user)) {
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err = nvgpu_nvs_ctrl_fifo_reserve_exclusive_user(g->sched_ctrl_fifo, user);
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if (err != 0) {
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return err;
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}
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}
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} else {
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if (args->queue_num != NVS_CTRL_FIFO_QUEUE_NUM_EVENT)
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return -EINVAL;
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if (args->direction != NVS_CTRL_FIFO_QUEUE_DIRECTION_SCHEDULER_TO_CLIENT)
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return -EINVAL;
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}
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return 0;
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}
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static enum nvgpu_nvs_ctrl_queue_num nvgpu_nvs_translate_queue_num(u32 queue_num_arg)
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{
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enum nvgpu_nvs_ctrl_queue_num num_queue = NVGPU_NVS_INVALID;
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if (queue_num_arg == NVGPU_NVS_CTRL_FIFO_QUEUE_NUM_CONTROL)
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num_queue = NVGPU_NVS_NUM_CONTROL;
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else if (queue_num_arg == NVS_CTRL_FIFO_QUEUE_NUM_EVENT)
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num_queue = NVGPU_NVS_NUM_EVENT;
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return num_queue;
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}
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static enum nvgpu_nvs_ctrl_queue_direction
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nvgpu_nvs_translate_queue_direction(u32 queue_direction)
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{
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enum nvgpu_nvs_ctrl_queue_direction direction = NVGPU_NVS_DIR_INVALID;
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if (queue_direction == NVS_CTRL_FIFO_QUEUE_DIRECTION_CLIENT_TO_SCHEDULER)
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direction = NVGPU_NVS_DIR_CLIENT_TO_SCHEDULER;
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else if (queue_direction == NVS_CTRL_FIFO_QUEUE_DIRECTION_SCHEDULER_TO_CLIENT)
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direction = NVGPU_NVS_DIR_SCHEDULER_TO_CLIENT;
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return direction;
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}
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static int nvgpu_nvs_ctrl_fifo_create_queue(struct gk20a *g,
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struct nvs_domain_ctrl_fifo_user *user,
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struct nvgpu_nvs_ctrl_fifo_ioctl_create_queue_args *args)
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{
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enum nvgpu_nvs_ctrl_queue_num num_queue;
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enum nvgpu_nvs_ctrl_queue_direction queue_direction;
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struct nvgpu_nvs_ctrl_queue *queue;
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struct nvgpu_nvs_linux_buf_priv *priv = NULL;
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int err = 0;
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int fd;
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int flag = O_CLOEXEC;
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bool read_only;
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size_t queue_size;
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u8 mask = 0;
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err = nvgpu_nvs_ctrl_fifo_create_queue_verify_flags(g, user, args);
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if (err != 0) {
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args->dmabuf_fd = -1;
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return err;
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}
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nvgpu_nvs_ctrl_fifo_lock_queues(g);
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num_queue = nvgpu_nvs_translate_queue_num(args->queue_num);
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queue_direction = nvgpu_nvs_translate_queue_direction(args->direction);
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queue = nvgpu_nvs_ctrl_fifo_get_queue(g->sched_ctrl_fifo, num_queue, queue_direction, &mask);
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if (queue == NULL) {
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err = -EOPNOTSUPP;
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goto fail;
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}
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read_only = (args->access_type == NVS_CTRL_FIFO_QUEUE_ACCESS_TYPE_EXCLUSIVE) ? false : true;
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if (read_only) {
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flag |= O_RDONLY;
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} else {
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flag |= O_RDWR;
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}
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/* Support for Read-Only Observers will be added later */
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if (read_only) {
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err = -EOPNOTSUPP;
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goto fail;
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}
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if (args->access_type == NVS_CTRL_FIFO_QUEUE_ACCESS_TYPE_EXCLUSIVE) {
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if (nvgpu_nvs_buffer_is_valid(g, queue)) {
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err = -EBUSY;
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goto fail;
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}
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}
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/* For event queue, prevent multiple subscription by the same user */
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if (nvgpu_nvs_ctrl_fifo_user_is_subscribed_to_queue(user, queue)) {
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err = -EEXIST;
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goto fail;
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}
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queue_size = NVS_QUEUE_DEFAULT_SIZE;
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/* Ensure, event queue is constructed only once across all users. */
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if (!nvgpu_nvs_buffer_is_valid(g, queue)) {
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err = nvgpu_nvs_get_buf_linux(g, queue, queue_size, mask, read_only);
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if (err != 0) {
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goto fail;
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}
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}
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priv = queue->priv;
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fd = dma_buf_fd(priv->dmabuf, flag);
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if (fd < 0) {
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/* Might have valid user vmas for previous event queue users */
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if (!nvgpu_nvs_buf_linux_is_mapped(g, queue)) {
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nvgpu_nvs_ctrl_fifo_erase_queue(g, queue);
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}
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err = fd;
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goto fail;
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}
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nvgpu_nvs_ctrl_fifo_user_subscribe_queue(user, queue);
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args->dmabuf_fd = fd;
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/* update the queue size correctly */
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args->queue_size = queue_size;
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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return 0;
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fail:
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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nvgpu_err(g, "failed");
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/* set dmabuf_fd to -1 for failure exclusively */
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args->dmabuf_fd = -1;
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return err;
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}
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static void nvgpu_nvs_ctrl_fifo_undo_create_queue(struct gk20a *g,
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struct nvs_domain_ctrl_fifo_user *user,
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struct nvgpu_nvs_ctrl_fifo_ioctl_create_queue_args *args)
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{
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enum nvgpu_nvs_ctrl_queue_num num_queue;
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enum nvgpu_nvs_ctrl_queue_direction queue_direction;
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struct nvgpu_nvs_ctrl_queue *queue;
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u8 mask = 0;
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nvgpu_nvs_ctrl_fifo_lock_queues(g);
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num_queue = nvgpu_nvs_translate_queue_num(args->queue_num);
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queue_direction = nvgpu_nvs_translate_queue_direction(args->direction);
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queue = nvgpu_nvs_ctrl_fifo_get_queue(g->sched_ctrl_fifo, num_queue, queue_direction, &mask);
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if (queue == NULL) {
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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return;
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}
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nvgpu_nvs_ctrl_fifo_user_unsubscribe_queue(user, queue);
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/* For Control Queues, no mappings exist, For Event Queues, mappings might exist */
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if (nvgpu_nvs_buffer_is_valid(g, queue) && !nvgpu_nvs_buf_linux_is_mapped(g, queue)) {
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nvgpu_nvs_ctrl_fifo_erase_queue(g, queue);
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}
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if (args->dmabuf_fd != 0) {
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put_unused_fd(args->dmabuf_fd);
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args->dmabuf_fd = 0;
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}
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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}
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static int nvgpu_nvs_ctrl_fifo_destroy_queue(struct gk20a *g,
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struct nvs_domain_ctrl_fifo_user *user,
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struct nvgpu_nvs_ctrl_fifo_ioctl_release_queue_args *args)
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{
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enum nvgpu_nvs_ctrl_queue_num num_queue;
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enum nvgpu_nvs_ctrl_queue_direction queue_direction;
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struct nvgpu_nvs_ctrl_queue *queue;
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bool is_exclusive_user;
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int err = 0;
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u8 mask = 0;
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if (args->reserve0 != 0) {
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return -EINVAL;
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}
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if (args->reserve1 != 0) {
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return -EINVAL;
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}
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if (args->reserve2 != 0) {
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return -EINVAL;
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}
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num_queue = nvgpu_nvs_translate_queue_num(args->queue_num);
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queue_direction = nvgpu_nvs_translate_queue_direction(args->direction);
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is_exclusive_user = nvgpu_nvs_ctrl_fifo_is_exclusive_user(g->sched_ctrl_fifo, user);
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if (!is_exclusive_user) {
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if ((num_queue == NVGPU_NVS_NUM_CONTROL) ||
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(queue_direction == NVGPU_NVS_DIR_CLIENT_TO_SCHEDULER)) {
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return -EPERM;
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}
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}
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queue = nvgpu_nvs_ctrl_fifo_get_queue(g->sched_ctrl_fifo, num_queue, queue_direction, &mask);
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if (queue == NULL) {
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err = -EOPNOTSUPP;
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goto fail;
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}
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nvgpu_nvs_ctrl_fifo_lock_queues(g);
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if (!nvgpu_nvs_ctrl_fifo_user_is_subscribed_to_queue(user, queue)) {
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err = -EPERM;
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goto fail;
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}
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/* For Control Queues, no mappings should exist, For Event Queues, mappings might exist */
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if (nvgpu_nvs_buffer_is_valid(g, queue)) {
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if (!nvgpu_nvs_buf_linux_is_mapped(g, queue)) {
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nvgpu_nvs_ctrl_fifo_erase_queue(g, queue);
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} else if (is_exclusive_user) {
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err = -EBUSY;
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goto fail;
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}
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}
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nvgpu_nvs_ctrl_fifo_user_unsubscribe_queue(user, queue);
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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return 0;
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fail:
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nvgpu_nvs_ctrl_fifo_unlock_queues(g);
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nvgpu_err(g, "failed to destroy queue");
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return err;
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}
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long nvgpu_nvs_ctrl_fifo_ops_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
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{
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u8 buf[NVGPU_NVS_CTRL_FIFO_IOCTL_MAX_ARG_SIZE] = { 0 };
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int err = 0;
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struct nvgpu_nvs_domain_ctrl_fifo_user_linux *linux_user;
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struct nvs_domain_ctrl_fifo_user *user;
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struct gk20a *g;
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linux_user = (struct nvgpu_nvs_domain_ctrl_fifo_user_linux *)filp->private_data;
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if (linux_user == NULL) {
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return -ENODEV;
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}
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user = &linux_user->user;
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g = nvgpu_get_gk20a_from_cdev(linux_user->cdev);
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nvs_dbg(g, "IOC_TYPE: %c", _IOC_TYPE(cmd));
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nvs_dbg(g, "IOC_NR: %u", _IOC_NR(cmd));
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nvs_dbg(g, "IOC_SIZE: %u", _IOC_SIZE(cmd));
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if ((_IOC_TYPE(cmd) != NVGPU_NVS_CTRL_FIFO_IOCTL_MAGIC) ||
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(_IOC_NR(cmd) == 0) ||
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(_IOC_NR(cmd) > NVGPU_NVS_CTRL_FIFO_IOCTL_LAST) ||
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(_IOC_SIZE(cmd) > NVGPU_NVS_CTRL_FIFO_IOCTL_MAX_ARG_SIZE)) {
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nvs_dbg(g, "-> BAD!!");
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return -EINVAL;
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}
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if (_IOC_DIR(cmd) & _IOC_WRITE) {
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if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
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return -EFAULT;
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}
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err = gk20a_busy(g);
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if (err != 0) {
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return err;
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}
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switch (cmd) {
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case NVGPU_NVS_CTRL_FIFO_CREATE_QUEUE:
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{
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struct nvgpu_nvs_ctrl_fifo_ioctl_create_queue_args *args =
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(struct nvgpu_nvs_ctrl_fifo_ioctl_create_queue_args *)buf;
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err = nvgpu_nvs_ctrl_fifo_create_queue(g, user, args);
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if (err)
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goto done;
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if (copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd))) {
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nvgpu_nvs_ctrl_fifo_undo_create_queue(g, user, args);
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err = -EFAULT;
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args->dmabuf_fd = -1;
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goto done;
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}
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break;
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}
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case NVGPU_NVS_CTRL_FIFO_RELEASE_QUEUE:
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{
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struct nvgpu_nvs_ctrl_fifo_ioctl_release_queue_args *args =
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(struct nvgpu_nvs_ctrl_fifo_ioctl_release_queue_args *)buf;
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err = nvgpu_nvs_ctrl_fifo_destroy_queue(g, user, args);
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if (err)
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goto done;
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break;
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}
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case NVGPU_NVS_CTRL_FIFO_ENABLE_EVENT:
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{
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err = -EOPNOTSUPP;
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goto done;
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}
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default:
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err = -ENOTTY;
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goto done;
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}
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done:
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gk20a_idle(g);
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return err;
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}
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