gpu: nvgpu: validate return of nvgpu_tsg_get_sm_error_state

nvgpu_tsg_get_sm_error_state already checks the sm_id and
tsg->sm_error_state. No need to check these before calling
nvgpu_tsg_get_sm_error_state.

CID 484927
CID 299106
Bug 3512546

Change-Id: I02a05d8686cf7027cfc271f470198e7985dc4e16
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2722470
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2022-05-31 15:21:13 +05:30
committed by mobile promotions
parent d177cae3fe
commit e80d74b810
2 changed files with 8 additions and 14 deletions

View File

@@ -283,8 +283,6 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
struct nvgpu_tsg *tsg; struct nvgpu_tsg *tsg;
u32 sm_id; u32 sm_id;
int err = 0; int err = 0;
struct nvgpu_gr_config *gr_config =
nvgpu_gr_get_gpu_instance_config_ptr(g, dbg_s->gpu_instance_id);
ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
if (ch == NULL) { if (ch == NULL) {
@@ -298,17 +296,14 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
} }
sm_id = args->sm_id; sm_id = args->sm_id;
if (sm_id >= nvgpu_gr_config_get_no_of_sm(gr_config)) {
return -EINVAL;
}
if (tsg->sm_error_states == NULL) {
return -EINVAL;
}
nvgpu_speculation_barrier(); nvgpu_speculation_barrier();
sm_error_state = nvgpu_tsg_get_sm_error_state(tsg, sm_id); sm_error_state = nvgpu_tsg_get_sm_error_state(tsg, sm_id);
if (sm_error_state == NULL) {
return -EINVAL;
}
sm_error_state_record.hww_global_esr = sm_error_state_record.hww_global_esr =
sm_error_state->hww_global_esr; sm_error_state->hww_global_esr;
sm_error_state_record.hww_warp_esr = sm_error_state_record.hww_warp_esr =

View File

@@ -629,17 +629,16 @@ static int gk20a_tsg_ioctl_read_single_sm_error_state(struct gk20a *g,
struct nvgpu_tsg_sm_error_state_record sm_error_state_record; struct nvgpu_tsg_sm_error_state_record sm_error_state_record;
u32 sm_id; u32 sm_id;
int err = 0; int err = 0;
struct nvgpu_gr_config *gr_config;
gr_config = nvgpu_gr_get_gpu_instance_config_ptr(g, gpu_instance_id);
sm_id = args->sm_id; sm_id = args->sm_id;
if (sm_id >= nvgpu_gr_config_get_no_of_sm(gr_config)) {
return -EINVAL;
}
nvgpu_speculation_barrier(); nvgpu_speculation_barrier();
sm_error_state = nvgpu_tsg_get_sm_error_state(tsg, sm_id); sm_error_state = nvgpu_tsg_get_sm_error_state(tsg, sm_id);
if (sm_error_state == NULL) {
return -EINVAL;
}
sm_error_state_record.global_esr = sm_error_state_record.global_esr =
sm_error_state->hww_global_esr; sm_error_state->hww_global_esr;
sm_error_state_record.warp_esr = sm_error_state_record.warp_esr =