From e848e9dfb850d6306abd5864662c929abfbdab0d Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Fri, 29 Mar 2019 07:03:02 +0530 Subject: [PATCH] gpu: nvgpu: prepare sec2 msg, allocator units SEC2 message handling unit can't be part of command handling unit as it creates circular dependencies with the SEC2 tasks (ACR bootstrap) SEC2 allocator unit shall encompass DMEM allocator and other allocators used by SEC2. JIRA NVGPU-2075 Change-Id: Ic2b8204d8225f2056785f035cbecdb776a9ecfe9 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2085749 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 2 + drivers/gpu/nvgpu/Makefile.sources | 2 + drivers/gpu/nvgpu/common/sec2/sec2.c | 5 +- .../gpu/nvgpu/common/sec2/sec2_allocator.c | 51 +++++ drivers/gpu/nvgpu/common/sec2/sec2_ipc.c | 184 ---------------- drivers/gpu/nvgpu/common/sec2/sec2_msg.c | 201 ++++++++++++++++++ drivers/gpu/nvgpu/common/sec2/sec2_queue.c | 3 +- drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 1 + drivers/gpu/nvgpu/include/nvgpu/sec2.h | 3 +- .../gpu/nvgpu/include/nvgpu/sec2/allocator.h | 35 +++ .../{sec2if/sec2_if_sec2.h => sec2/msg.h} | 30 ++- .../nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h | 12 +- drivers/gpu/nvgpu/tu104/sec2_tu104.c | 1 + 13 files changed, 322 insertions(+), 208 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/sec2/sec2_allocator.c create mode 100644 drivers/gpu/nvgpu/common/sec2/sec2_msg.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/sec2/allocator.h rename drivers/gpu/nvgpu/include/nvgpu/{sec2if/sec2_if_sec2.h => sec2/msg.h} (80%) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 44936e098..aa70726a2 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -448,7 +448,9 @@ nvgpu-y += \ common/engine_queues/engine_fb_queue.o \ common/init/hal_init.o \ common/sec2/sec2.o \ + common/sec2/sec2_allocator.o \ common/sec2/sec2_ipc.o \ + common/sec2/sec2_msg.o \ common/sec2/sec2_queue.o \ common/sec2/sec2_seq.o \ common/io/io.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index e149cf131..f72a99fae 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -160,7 +160,9 @@ srcs += common/sim.c \ common/acr/acr_sw_gv11b.c \ common/acr/acr_sw_tu104.c \ common/sec2/sec2.c \ + common/sec2/sec2_allocator.c \ common/sec2/sec2_ipc.c \ + common/sec2/sec2_msg.c \ common/sec2/sec2_queue.c \ common/sec2/sec2_seq.c \ common/ptimer/ptimer.c \ diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index 592c9789c..cf31f81f4 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -27,8 +27,9 @@ #include #include #include -#include #include +#include +#include static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2) { @@ -96,6 +97,8 @@ int nvgpu_sec2_destroy(struct gk20a *g) nvgpu_log_fn(g, " "); + nvgpu_sec2_dmem_allocator_destroy(&sec2->dmem); + nvgpu_mutex_acquire(&sec2->isr_mutex); sec2->isr_enabled = false; nvgpu_mutex_release(&sec2->isr_mutex); diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_allocator.c b/drivers/gpu/nvgpu/common/sec2/sec2_allocator.c new file mode 100644 index 000000000..534df3df8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2_allocator.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +void nvgpu_sec2_dmem_allocator_init(struct gk20a *g, + struct nvgpu_allocator *dmem, + struct sec2_init_msg_sec2_init *sec2_init) +{ + if (!nvgpu_alloc_initialized(dmem)) { + /* Align start and end addresses */ + u32 start = ALIGN(sec2_init->nv_managed_area_offset, + PMU_DMEM_ALLOC_ALIGNMENT); + + u32 end = (sec2_init->nv_managed_area_offset + + sec2_init->nv_managed_area_size) & + ~(PMU_DMEM_ALLOC_ALIGNMENT - 1U); + u32 size = end - start; + + nvgpu_bitmap_allocator_init(g, dmem, "sec2_dmem", + start, size, PMU_DMEM_ALLOC_ALIGNMENT, 0U); + } +} + +void nvgpu_sec2_dmem_allocator_destroy(struct nvgpu_allocator *dmem) +{ + if (nvgpu_alloc_initialized(dmem)) { + nvgpu_alloc_destroy(dmem); + } +} diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c index 66ab590d4..fdb2f187e 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c @@ -29,7 +29,6 @@ #include #include #include -#include #include /* command post operation functions */ @@ -145,189 +144,6 @@ exit: return err; } -/* Message/Event request handlers */ -static int sec2_response_handle(struct nvgpu_sec2 *sec2, - struct nv_flcn_msg_sec2 *msg) -{ - struct gk20a *g = sec2->g; - - return nvgpu_sec2_seq_response_handle(g, &sec2->sequences, - msg, msg->hdr.seq_id); -} - -static int sec2_handle_event(struct nvgpu_sec2 *sec2, - struct nv_flcn_msg_sec2 *msg) -{ - int err = 0; - - switch (msg->hdr.unit_id) { - default: - break; - } - - return err; -} - -static bool sec2_read_message(struct nvgpu_sec2 *sec2, - u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status) -{ - struct gk20a *g = sec2->g; - u32 read_size; - int err; - - *status = 0; - - if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) { - return false; - } - - if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, - &sec2->flcn, &msg->hdr, - PMU_MSG_HDR_SIZE, status)) { - nvgpu_err(g, "fail to read msg from queue %d", queue_id); - goto clean_up; - } - - if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) { - err = nvgpu_sec2_queue_rewind(&sec2->flcn, - sec2->queues, queue_id); - if (err != 0) { - nvgpu_err(g, "fail to rewind queue %d", queue_id); - *status = err; - goto clean_up; - } - - /* read again after rewind */ - if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, - &sec2->flcn, &msg->hdr, - PMU_MSG_HDR_SIZE, status)) { - nvgpu_err(g, "fail to read msg from queue %d", - queue_id); - goto clean_up; - } - } - - if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) { - nvgpu_err(g, "read invalid unit_id %d from queue %d", - msg->hdr.unit_id, queue_id); - *status = -EINVAL; - goto clean_up; - } - - if (msg->hdr.size > PMU_MSG_HDR_SIZE) { - read_size = msg->hdr.size - PMU_MSG_HDR_SIZE; - if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, - &sec2->flcn, &msg->msg, - read_size, status)) { - nvgpu_err(g, "fail to read msg from queue %d", - queue_id); - goto clean_up; - } - } - - return true; - -clean_up: - return false; -} - -static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, - struct nv_flcn_msg_sec2 *msg) -{ - struct gk20a *g = sec2->g; - struct sec2_init_msg_sec2_init *sec2_init; - u32 tail = 0; - int err = 0; - - g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET); - - err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail, - (u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U); - if (err != 0) { - goto exit; - } - - if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) { - nvgpu_err(g, "expecting init msg"); - err = -EINVAL; - goto exit; - } - - err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE, - (u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U); - if (err != 0) { - goto exit; - } - - if (msg->msg.init.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) { - nvgpu_err(g, "expecting init msg"); - err = -EINVAL; - goto exit; - } - - tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT); - g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET); - - sec2_init = &msg->msg.init.sec2_init; - - err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init); - if (err != 0) { - return err; - } - - if (!nvgpu_alloc_initialized(&sec2->dmem)) { - /* Align start and end addresses */ - u32 start = ALIGN(sec2_init->nv_managed_area_offset, - PMU_DMEM_ALLOC_ALIGNMENT); - - u32 end = (sec2_init->nv_managed_area_offset + - sec2_init->nv_managed_area_size) & - ~(PMU_DMEM_ALLOC_ALIGNMENT - 1U); - u32 size = end - start; - - nvgpu_bitmap_allocator_init(g, &sec2->dmem, "sec2_dmem", - start, size, PMU_DMEM_ALLOC_ALIGNMENT, 0U); - } - - sec2->sec2_ready = true; - -exit: - return err; -} - -int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2) -{ - struct gk20a *g = sec2->g; - struct nv_flcn_msg_sec2 msg; - int status = 0; - - if (unlikely(!sec2->sec2_ready)) { - status = sec2_process_init_msg(sec2, &msg); - goto exit; - } - - while (sec2_read_message(sec2, - SEC2_NV_MSGQ_LOG_ID, &msg, &status)) { - - nvgpu_sec2_dbg(g, "read msg hdr: "); - nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x", - msg.hdr.unit_id, msg.hdr.size); - nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x", - msg.hdr.ctrl_flags, msg.hdr.seq_id); - - msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK; - - if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) { - sec2_handle_event(sec2, &msg); - } else { - sec2_response_handle(sec2, &msg); - } - } - -exit: - return status; -} - int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, void *var, u8 val) { diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_msg.c b/drivers/gpu/nvgpu/common/sec2/sec2_msg.c new file mode 100644 index 000000000..3a7f681f0 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2_msg.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Message/Event request handlers */ +static int sec2_response_handle(struct nvgpu_sec2 *sec2, + struct nv_flcn_msg_sec2 *msg) +{ + struct gk20a *g = sec2->g; + + return nvgpu_sec2_seq_response_handle(g, &sec2->sequences, + msg, msg->hdr.seq_id); +} + +static int sec2_handle_event(struct nvgpu_sec2 *sec2, + struct nv_flcn_msg_sec2 *msg) +{ + int err = 0; + + switch (msg->hdr.unit_id) { + default: + break; + } + + return err; +} + +static bool sec2_read_message(struct nvgpu_sec2 *sec2, + u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status) +{ + struct gk20a *g = sec2->g; + u32 read_size; + int err; + + *status = 0U; + + if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) { + return false; + } + + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->hdr, + PMU_MSG_HDR_SIZE, status)) { + nvgpu_err(g, "fail to read msg from queue %d", queue_id); + goto clean_up; + } + + if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) { + err = nvgpu_sec2_queue_rewind(&sec2->flcn, + sec2->queues, queue_id); + if (err != 0) { + nvgpu_err(g, "fail to rewind queue %d", queue_id); + *status = err; + goto clean_up; + } + + /* read again after rewind */ + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->hdr, + PMU_MSG_HDR_SIZE, status)) { + nvgpu_err(g, "fail to read msg from queue %d", + queue_id); + goto clean_up; + } + } + + if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) { + nvgpu_err(g, "read invalid unit_id %d from queue %d", + msg->hdr.unit_id, queue_id); + *status = -EINVAL; + goto clean_up; + } + + if (msg->hdr.size > PMU_MSG_HDR_SIZE) { + read_size = msg->hdr.size - PMU_MSG_HDR_SIZE; + if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id, + &sec2->flcn, &msg->msg, + read_size, status)) { + nvgpu_err(g, "fail to read msg from queue %d", + queue_id); + goto clean_up; + } + } + + return true; + +clean_up: + return false; +} + +static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, + struct nv_flcn_msg_sec2 *msg) +{ + struct gk20a *g = sec2->g; + struct sec2_init_msg_sec2_init *sec2_init; + u32 tail = 0; + int err = 0; + + g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET); + + err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail, + (u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U); + if (err != 0) { + goto exit; + } + + if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) { + nvgpu_err(g, "expecting init msg"); + err = -EINVAL; + goto exit; + } + + err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE, + (u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U); + if (err != 0) { + goto exit; + } + + if (msg->msg.init.msg_type != NV_SEC2_INIT_MSG_ID_SEC2_INIT) { + nvgpu_err(g, "expecting init msg"); + err = -EINVAL; + goto exit; + } + + tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT); + g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET); + + sec2_init = &msg->msg.init.sec2_init; + + err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init); + if (err != 0) { + return err; + } + + nvgpu_sec2_dmem_allocator_init(g, &sec2->dmem, sec2_init); + + sec2->sec2_ready = true; + +exit: + return err; +} + +int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2) +{ + struct gk20a *g = sec2->g; + struct nv_flcn_msg_sec2 msg; + int status = 0; + + if (unlikely(!sec2->sec2_ready)) { + status = sec2_process_init_msg(sec2, &msg); + goto exit; + } + + while (sec2_read_message(sec2, + SEC2_NV_MSGQ_LOG_ID, &msg, &status)) { + + nvgpu_sec2_dbg(g, "read msg hdr: "); + nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x", + msg.hdr.unit_id, msg.hdr.size); + nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x", + msg.hdr.ctrl_flags, msg.hdr.seq_id); + + msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK; + + if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) { + sec2_handle_event(sec2, &msg); + } else { + sec2_response_handle(sec2, &msg); + } + } + +exit: + return status; +} diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_queue.c b/drivers/gpu/nvgpu/common/sec2/sec2_queue.c index 84eee1e4d..ca1f249dd 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_queue.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_queue.c @@ -20,11 +20,10 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include -#include #include #include +#include #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h index 3a4fe726b..c9ca19ef4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h @@ -24,6 +24,7 @@ #define NVGPU_FLCNIF_CMN_H #include +#include #define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0U diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index 950c58a83..c59e61942 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -32,9 +32,9 @@ #include #include #include +#include #include -#include #define nvgpu_sec2_dbg(g, fmt, args...) \ nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) @@ -72,7 +72,6 @@ struct nvgpu_sec2 { int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, u32 queue_id, sec2_callback callback, void *cb_param, u32 timeout); -int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2); int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, void *var, u8 val); diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/allocator.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/allocator.h new file mode 100644 index 000000000..8eff1020f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/allocator.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_SEC2_ALLOCATOR_H +#define NVGPU_SEC2_ALLOCATOR_H + +struct gk20a; +struct nvgpu_allocator; +struct sec2_init_msg_sec2_init; + +void nvgpu_sec2_dmem_allocator_init(struct gk20a *g, + struct nvgpu_allocator *dmem, + struct sec2_init_msg_sec2_init *sec2_init); +void nvgpu_sec2_dmem_allocator_destroy(struct nvgpu_allocator *dmem); + +#endif /* NVGPU_SEC2_ALLOCATOR_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h similarity index 80% rename from drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h rename to drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h index a29451165..a898a209d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h @@ -20,14 +20,18 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_SEC2_IF_SEC2_H -#define NVGPU_SEC2_IF_SEC2_H +#ifndef NVGPU_SEC2_MSG_H +#define NVGPU_SEC2_MSG_H +#include #include +#include #include +struct nvgpu_sec2; + /* - * SEC2 Command/Message Interfaces - SEC2 Management + * SEC2 Message Interfaces - SEC2 Management */ /* @@ -35,8 +39,7 @@ * messages. * _SEC2_INIT - sec2_init_msg_sec2_init */ -enum -{ +enum { NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U, }; @@ -46,8 +49,7 @@ struct sec2_init_msg_sec2_init { u16 os_debug_entry_point; - struct - { + struct { u32 queue_offset; u16 queue_size; u8 queue_phy_id; @@ -63,4 +65,16 @@ union nv_flcn_msg_sec2_init { struct sec2_init_msg_sec2_init sec2_init; }; -#endif /* NVGPU_SEC2_IF_SEC2_H */ + +struct nv_flcn_msg_sec2 { + struct pmu_hdr hdr; + + union { + union nv_flcn_msg_sec2_init init; + union nv_sec2_acr_msg acr; + } msg; +}; + +int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2); + +#endif /* NVGPU_SEC2_MSG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h index 839743fc5..415fb7f23 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,6 @@ #ifndef NVGPU_SEC2_CMD_IF_H #define NVGPU_SEC2_CMD_IF_H -#include #include struct nv_flcn_cmd_sec2 { @@ -33,15 +32,6 @@ struct nv_flcn_cmd_sec2 { } cmd; }; -struct nv_flcn_msg_sec2 { - struct pmu_hdr hdr; - - union { - union nv_flcn_msg_sec2_init init; - union nv_sec2_acr_msg acr; - } msg; -}; - #define NV_SEC2_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND #define NV_SEC2_UNIT_INIT (0x01U) #define NV_SEC2_UNIT_ACR (0x07U) diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.c b/drivers/gpu/nvgpu/tu104/sec2_tu104.c index 310bf8693..bbaf15311 100644 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.c +++ b/drivers/gpu/nvgpu/tu104/sec2_tu104.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "sec2_tu104.h"