From e852ea6f2ac0edbd38ade251c0365f3409b46da7 Mon Sep 17 00:00:00 2001
From: Seshendra Gadagottu <sgadagottu@nvidia.com>
Date: Thu, 2 May 2019 16:41:46 -0700
Subject: [PATCH] gpu: nvgpu: fix MISRA directive 4.10 in gr falcon

Use correct header files guard for gr_falcon_priv.h

JIRA NVGPU-3226

Change-Id: Ibdea01ba697017b70c23e0245ba7f9dbe33d7dac
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110735
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
index 50139542a..9ed233128 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
+++ b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
@@ -21,7 +21,7 @@
  */
 
 #ifndef GR_FALCON_PRIV_H
-#define GR_FALOCN_PRIV_H
+#define GR_FALCON_PRIV_H
 
 #include <nvgpu/types.h>
 #include <nvgpu/nvgpu_mem.h>
@@ -125,5 +125,5 @@ enum {
 #define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED	0x393161daU
 
 
-#endif /* GR_FALOCN_PRIV_H */
+#endif /* GR_FALCON_PRIV_H */