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gpu: nvgpu: add channel event id support

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With NVGPU_IOCTL_CHANNEL_EVENTS_CTRL, nvgpu can
raise events to User space. But user space
cannot distinguish between various types of events.
To overcome this, we need finer-grained API to
deliver various events to user space.

Remove old API NVGPU_IOCTL_CHANNEL_EVENTS_CTRL,
and all the support for this API (we can remove
this since User space has not started using this
API at all)

Add new API NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL
which will accept an event_id (like BPT.INT or
BPT.PAUSE), a command to enable the event,
and return a file descriptor on which
we can raise the event (if cmd=enable)
Event is disabled when file descriptor is closed

Add file operations "gk20a_event_id_ops"
to support polling on event fd

Also add API gk20a_channel_get_event_data_from_id()
to get event_data of event from its id

Bug 200089620

Change-Id: I5288f19f38ff49448c46338c33b2a927c9e02254
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1030775
(cherry picked from commit 5721ce2735950440bedc2b86f851db08ed593275)
Reviewed-on: http://git-master/r/1120318
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-03-31 12:33:19 +05:30
committed by Terje Bergstrom
parent 76ab6c1e5b
commit e87ba53235
6 changed files with 177 additions and 121 deletions
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29
include/uapi/linux/nvgpu.h
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@@ -825,17 +825,6 @@ struct nvgpu_notification {
#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1
};
/* Enable/disable/clear event notifications */
struct nvgpu_channel_events_ctrl_args {
__u32 cmd; /* in */
__u32 _pad0[1];
};
/* valid event ctrl values */
#define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_DISABLE 0
#define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_ENABLE 1
#define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_CLEAR 2
/* cycle stats snapshot buffer support for mode E */
struct nvgpu_cycle_stats_snapshot_args {
__u32 cmd; /* in: command to handle */
@@ -886,6 +875,20 @@ struct nvgpu_timeslice_args {
__u32 reserved;
};
struct nvgpu_event_id_ctrl_args {
__u32 cmd; /* in */
__u32 event_id; /* in */
__s32 event_fd; /* out */
__u32 padding;
};
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 5
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1
#define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \
_IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args)
#define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \
@@ -922,8 +925,8 @@ struct nvgpu_timeslice_args {
_IO(NVGPU_IOCTL_MAGIC, 115)
#define NVGPU_IOCTL_CHANNEL_FORCE_RESET \
_IO(NVGPU_IOCTL_MAGIC, 116)
#define NVGPU_IOCTL_CHANNEL_EVENTS_CTRL \
_IOW(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_channel_events_ctrl_args)
#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \
_IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args)
#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \
_IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args)
#define NVGPU_IOCTL_CHANNEL_WDT \