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gpu: nvgpu: Restructure nvgpu.common.volt

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This patch does the following.
1. Remove unused functions from volt_pmu.c.
2. Append public functions with nvgpu.
3. Remove GP106 functions and rename TU104 to generic functions.
4. Rename volt struct from gpu_ops.
5. Remove the unused volt.h header file.
6. Make local functions as static and put in order.
7. Remove unused inclusion on header files.
8. After 4, generic functions can be called directly instead of g->ops.

Jira NVGPU-1956

Change-Id: Icaea0ca817d37cccfc09241baa2f047ec2688169
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076535
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-03-21 14:34:02 +05:30
committed by mobile promotions
parent 64269c2c55
commit e943e6278a
17 changed files with 279 additions and 602 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/pmu/clk/clk.c
View File

@@ -914,7 +914,7 @@ int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g)
}
voltuv = gpcclk_voltuv;
status = volt_set_voltage(g, voltuv, 0);
status = nvgpu_volt_set_voltage(g, voltuv, 0);
if (status != 0) {
nvgpu_err(g,
"attempt to set boot voltage failed %d",
@@ -963,7 +963,7 @@ int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g)
voltuv = gpcclk_voltuv;
status = volt_set_voltage(g, voltuv, 0U);
status = nvgpu_volt_set_voltage(g, voltuv, 0U);
if (status != 0) {
nvgpu_err(g, "attempt to set max voltage failed %d", voltuv);
}
@@ -1028,7 +1028,7 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
status = clk_domain_freq_to_volt(g, gpcclk_domain,
&gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
status = g->ops.pmu_ver.volt.volt_get_vmin(g, &vmin_uv);
status = nvgpu_volt_get_vmin_ps35(g, &vmin_uv);
if(status != 0)
{
nvgpu_pmu_dbg(g, "Get vmin failed, proceeding with freq_to_volt value");
@@ -1068,7 +1068,7 @@ int clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx,
int status = -EINVAL;
(void)memset(&rpc, 0, sizeof(struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt ));
rpc.volt_rail_idx = volt_rail_volt_domain_convert_to_idx(g, railidx);
rpc.volt_rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g, railidx);
rpc.clk_domain_idx = clkdomain_idx;
rpc.voltage_type = CTRL_VOLT_DOMAIN_LOGIC;
rpc.input.value = *pvoltuv;
@@ -1089,7 +1089,7 @@ int clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx,
int status = -EINVAL;
(void)memset(&rpc, 0, sizeof(struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt ));
rpc.volt_rail_idx = volt_rail_volt_domain_convert_to_idx(g, railidx);
rpc.volt_rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g, railidx);
rpc.clk_domain_idx = clkdomain_idx;
rpc.voltage_type = CTRL_VOLT_DOMAIN_LOGIC;
rpc.input.value = *pclkmhz;

2
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -615,7 +615,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
}
gpcclk_voltuv += vmargin_uv;
status = g->ops.pmu_ver.volt.volt_get_vmin(g, &vmin_uv);
status = nvgpu_volt_get_vmin_ps35(g, &vmin_uv);
if (status != 0) {
nvgpu_err(g, "Failed to execute Vmin get_status status=0x%x",
status);

2
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -747,7 +747,7 @@ int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv)
int status = 0;
u8 vmargin_idx;
vmargin_idx = g->ops.pmu_ver.volt.volt_get_vmargin(g);
vmargin_idx = nvgpu_volt_get_vmargin_ps35(g);
if (vmargin_idx == 0U) {
return 0;
}

16
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -1337,12 +1337,6 @@ static int init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu, u32 app_version)
boardobjgrp_pmugetstatus_impl_v1;
g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid =
is_boardobjgrp_pmucmd_id_valid_v1;
g->ops.pmu_ver.volt.volt_set_voltage =
nvgpu_volt_set_voltage_gv10x;
g->ops.pmu_ver.volt.volt_get_voltage =
nvgpu_volt_rail_get_voltage_gv10x;
g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu =
nvgpu_volt_send_load_cmd_to_pmu_gv10x;
g->ops.pmu_ver.clk.get_vbios_clk_domain =
nvgpu_clk_get_vbios_clk_domain_gv10x;
g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =
@@ -1354,10 +1348,6 @@ static int init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu, u32 app_version)
nvgpu_clk_set_boot_fll_clk_gv10x;
} else {
g->ops.pmu_ver.clk.clk_set_boot_clk = NULL;
g->ops.pmu_ver.volt.volt_get_vmin =
nvgpu_volt_get_vmin_tu10x;
g->ops.pmu_ver.volt.volt_get_vmargin =
nvgpu_volt_get_vmargin_tu10x;
}
} else {
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
@@ -1518,12 +1508,6 @@ static int init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu, u32 app_version)
boardobjgrp_pmugetstatus_impl;
g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid =
is_boardobjgrp_pmucmd_id_valid_v0;
g->ops.pmu_ver.volt.volt_set_voltage =
nvgpu_volt_set_voltage_gp10x;
g->ops.pmu_ver.volt.volt_get_voltage =
nvgpu_volt_rail_get_voltage_gp10x;
g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu =
nvgpu_volt_send_load_cmd_to_pmu_gp10x;
g->ops.pmu_ver.clk.get_vbios_clk_domain =
nvgpu_clk_get_vbios_clk_domain_gp10x;
g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =

15
drivers/gpu/nvgpu/common/pmu/pstate/pstate.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/pmu/pmgr.h>
#include <nvgpu/pmu/therm.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "pstate.h"
@@ -79,17 +80,17 @@ int gk20a_init_pstate_support(struct gk20a *g)
goto err_therm_pmu_init_pmupstate;
}
err = volt_rail_sw_setup(g);
err = nvgpu_volt_rail_sw_setup(g);
if (err != 0) {
goto err_pmgr_pmu_init_pmupstate;
}
err = volt_dev_sw_setup(g);
err = nvgpu_volt_dev_sw_setup(g);
if (err != 0) {
goto err_pmgr_pmu_init_pmupstate;
}
err = volt_policy_sw_setup(g);
err = nvgpu_volt_policy_sw_setup(g);
if (err != 0) {
goto err_pmgr_pmu_init_pmupstate;
}
@@ -208,22 +209,22 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
}
}
err = volt_rail_pmu_setup(g);
err = nvgpu_volt_rail_pmu_setup(g);
if (err != 0) {
return err;
}
err = volt_dev_pmu_setup(g);
err = nvgpu_volt_dev_pmu_setup(g);
if (err != 0) {
return err;
}
err = volt_policy_pmu_setup(g);
err = nvgpu_volt_policy_pmu_setup(g);
if (err != 0) {
return err;
}
err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g);
err = nvgpu_volt_send_load_cmd_to_pmu(g);
if (err != 0) {
nvgpu_err(g,
"Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.",

28
drivers/gpu/nvgpu/common/pmu/volt/volt.h
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_VOLT_VOLT_H
#define NVGPU_VOLT_VOLT_H
#define VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID 0xFF
#endif /* NVGPU_VOLT_VOLT_H */

18
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
View File

@@ -31,15 +31,9 @@
#include <nvgpu/string.h>
#include <nvgpu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_dev.h"
#include "volt_rail.h"
#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U
#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U
static int volt_device_pmu_data_init_super(struct gk20a *g,
struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
@@ -266,7 +260,7 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g,
BIOS_GET_FIELD(s32, p_bios_entry->param4,
NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE);
volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
volt_domain = nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(g,
(u8)p_bios_entry->volt_domain);
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
nvgpu_err(g, "invalid voltage domain = %d",
@@ -490,7 +484,7 @@ static int volt_device_state_init(struct gk20a *g,
/* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
/* If VOLT_RAIL isn't supported, exit. */
if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu->volt)) {
rail_idx = volt_rail_volt_domain_convert_to_idx(g,
rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g,
pvolt_dev->volt_domain);
if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
nvgpu_err(g,
@@ -507,7 +501,7 @@ static int volt_device_state_init(struct gk20a *g,
goto done;
}
status = volt_rail_volt_dev_register(g, pRail,
status = nvgpu_volt_rail_volt_dev_register(g, pRail,
BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type);
if (status != 0) {
nvgpu_err(g,
@@ -524,7 +518,7 @@ done:
return status;
}
int volt_dev_pmu_setup(struct gk20a *g)
int nvgpu_volt_dev_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
@@ -543,7 +537,7 @@ int volt_dev_pmu_setup(struct gk20a *g)
return status;
}
int volt_dev_sw_setup(struct gk20a *g)
int nvgpu_volt_dev_sw_setup(struct gk20a *g)
{
int status = 0;
struct boardobjgrp *pboardobjgrp = NULL;

5
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,9 @@
#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1U
#define VOLTAGE_TABLE_MAX_ENTRIES 256U
#define VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID 0xFFU
#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U
#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U
struct voltage_device {
struct boardobj super;

355
drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.c
View File

@@ -29,121 +29,28 @@
#include <nvgpu/pmuif/ctrlperf.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_rail.h"
#include "volt_pmu.h"
#define RAIL_COUNT_GP 2
#define RAIL_COUNT_GV 1
struct volt_rpc_pmucmdhandler_params {
struct nv_pmu_volt_rpc *prpc_call;
u32 success;
};
static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 handle, u32 status)
{
struct volt_rpc_pmucmdhandler_params *phandlerparams =
(struct volt_rpc_pmucmdhandler_params *)param;
nvgpu_log_info(g, " ");
if (msg->msg.volt.msg_type != NV_PMU_VOLT_MSG_ID_RPC) {
nvgpu_err(g, "unsupported msg for VOLT RPC %x",
msg->msg.volt.msg_type);
return;
}
if (phandlerparams->prpc_call->b_supported) {
phandlerparams->success = 1;
}
}
static int volt_pmu_rpc_execute(struct gk20a *g,
struct nv_pmu_volt_rpc *prpc_call)
{
struct pmu_cmd cmd;
struct pmu_payload payload;
int status = 0;
u32 seqdesc;
struct volt_rpc_pmucmdhandler_params handler;
(void) memset(&payload, 0, sizeof(struct pmu_payload));
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
(void) memset(&handler, 0,
sizeof(struct volt_rpc_pmucmdhandler_params));
cmd.hdr.unit_id = PMU_UNIT_VOLT;
cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) +
(u32)sizeof(struct pmu_hdr);
cmd.cmd.volt.cmd_type = NV_PMU_VOLT_CMD_ID_RPC;
payload.in.buf = (u8 *)prpc_call;
payload.in.size = (u32)sizeof(struct nv_pmu_volt_rpc);
payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
payload.in.offset = NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET;
payload.out.buf = (u8 *)prpc_call;
payload.out.size = (u32)sizeof(struct nv_pmu_volt_rpc);
payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
payload.out.offset = NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET;
handler.prpc_call = prpc_call;
handler.success = 0;
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
volt_rpc_pmucmdhandler, (void *)&handler,
&seqdesc);
if (status != 0) {
nvgpu_err(g, "unable to post volt RPC cmd %x",
cmd.cmd.volt.cmd_type);
goto volt_pmu_rpc_execute;
}
pmu_wait_message_cond(&g->pmu,
gk20a_get_gr_idle_timeout(g),
&handler.success, 1);
if (handler.success == 0U) {
status = -EINVAL;
nvgpu_err(g, "rpc call to volt failed");
}
volt_pmu_rpc_execute:
return status;
}
int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
{
struct nv_pmu_volt_rpc rpc_call = { 0 };
int status = 0;
rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status != 0) {
nvgpu_err(g,
"Error while executing LOAD RPC: status = 0x%08x.",
status);
}
return status;
}
int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
static int volt_set_voltage_rpc(struct gk20a *g, u8 client_id,
struct ctrl_volt_volt_rail_list_v1 *prail_list)
{
struct nvgpu_pmu *pmu = &g->pmu;
struct nv_pmu_rpc_struct_volt_load rpc;
struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc;
int status = 0;
(void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
(void) memset(&rpc, 0,
sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage));
rpc.client_id = 0x1;
rpc.rail_list = *prail_list;
PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0);
if (status != 0) {
nvgpu_err(g, "Failed to execute RPC status=0x%x",
status);
@@ -152,41 +59,7 @@ int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
return status;
}
int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv)
{
struct nv_pmu_volt_rpc rpc_call = { 0 };
int status = 0;
u8 rail_idx;
rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu->volt, rail_idx))) {
nvgpu_err(g,
"failed: volt_domain = %d, voltage rail table = %d.",
volt_domain, rail_idx);
return -EINVAL;
}
/* Set RPC parameters. */
rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE;
rpc_call.params.volt_rail_get_voltage.rail_idx = rail_idx;
/* Execute the voltage get request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status != 0) {
nvgpu_err(g,
"Error while executing volt_rail_get_voltage rpc");
return status;
}
/* Copy out the current voltage. */
*pvoltage_uv = rpc_call.params.volt_rail_get_voltage.voltage_uv;
return status;
}
int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
static int volt_rail_get_voltage(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv)
{
struct nvgpu_pmu *pmu = &g->pmu;
@@ -194,7 +67,7 @@ int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
int status = 0;
u8 rail_idx;
rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g, volt_domain);
if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu->volt, rail_idx))) {
nvgpu_err(g,
@@ -218,72 +91,33 @@ int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
return status;
}
static int volt_policy_set_voltage(struct gk20a *g, u8 client_id,
struct ctrl_perf_volt_rail_list *prail_list)
static int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv)
{
struct nv_pmu_volt_rpc rpc_call = { 0 };
struct obj_volt *pvolt = &g->perf_pmu->volt;
int status = 0;
u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID;
u8 i = 0;
struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 };
/* Sanity check input rail list. */
for (i = 0; i < prail_list->num_rails; i++) {
if ((prail_list->rails[i].volt_domain ==
CTRL_VOLT_DOMAIN_INVALID) ||
(prail_list->rails[i].voltage_uv ==
NV_PMU_VOLT_VALUE_0V_IN_UV)) {
nvgpu_err(g, "Invalid voltage domain or target");
nvgpu_err(g, " client_id = %d, listEntry = %d",
client_id, i);
nvgpu_err(g, " volt_domain = %d, voltage_uv = %d uV.",
prail_list->rails[i].volt_domain,
prail_list->rails[i].voltage_uv);
status = -EINVAL;
goto exit;
}
}
rail_list.num_rails = RAIL_COUNT_GV;
rail_list.rails[0].rail_idx =
nvgpu_volt_rail_volt_domain_convert_to_idx(g,
CTRL_VOLT_DOMAIN_LOGIC);
rail_list.rails[0].voltage_uv = logic_voltage_uv;
rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
/* Convert the client ID to index. */
if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) {
policy_idx =
pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
}
else {
status = -EINVAL;
goto exit;
}
status = volt_set_voltage_rpc(g,
CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
/* Set RPC parameters. */
rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE;
rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx;
nvgpu_memcpy((u8 *)&rpc_call.params.volt_policy_voltage_data.rail_list,
(u8 *)prail_list, (sizeof(struct ctrl_perf_volt_rail_list)));
/* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status != 0) {
nvgpu_err(g,
"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
}
exit:
return status;
}
static int volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
struct ctrl_volt_volt_rail_list_v1 *prail_list)
int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g)
{
struct nvgpu_pmu *pmu = &g->pmu;
struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc;
struct nv_pmu_rpc_struct_volt_load rpc;
int status = 0;
(void) memset(&rpc, 0,
sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage));
rpc.client_id = 0x1;
rpc.rail_list = *prail_list;
PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0);
(void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
if (status != 0) {
nvgpu_err(g, "Failed to execute RPC status=0x%x",
status);
@@ -292,139 +126,14 @@ static int volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
return status;
}
int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv)
int nvgpu_volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
{
int status = 0;
struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 };
rail_list.num_rails = RAIL_COUNT_GV;
rail_list.rails[0].rail_idx =
volt_rail_volt_domain_convert_to_idx(g,
CTRL_VOLT_DOMAIN_LOGIC);
rail_list.rails[0].voltage_uv = logic_voltage_uv;
rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
status = volt_set_voltage_gv10x_rpc(g,
CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
return status;
}
int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv)
{
int status = 0;
struct ctrl_perf_volt_rail_list rail_list = { 0 };
rail_list.num_rails = RAIL_COUNT_GP;
rail_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
rail_list.rails[0].voltage_uv = logic_voltage_uv;
rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
rail_list.rails[1].volt_domain = CTRL_VOLT_DOMAIN_SRAM;
rail_list.rails[1].voltage_uv = sram_voltage_uv;
rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv;
status = volt_policy_set_voltage(g,
CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
return status;
}
int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
{
return g->ops.pmu_ver.volt.volt_set_voltage(g,
return volt_set_voltage(g,
logic_voltage_uv, sram_voltage_uv);
}
int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
int nvgpu_volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
{
return g->ops.pmu_ver.volt.volt_get_voltage(g,
volt_domain, voltage_uv);
}
static int volt_policy_set_noiseaware_vmin(struct gk20a *g,
struct ctrl_volt_volt_rail_list *prail_list)
{
struct nv_pmu_volt_rpc rpc_call = { 0 };
int status = 0;
/* Set RPC parameters. */
rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN;
rpc_call.params.volt_rail_set_noise_unaware_vmin.num_rails =
prail_list->num_rails;
nvgpu_memcpy(
(u8 *)&rpc_call.params.volt_rail_set_noise_unaware_vmin.rail_list,
(u8 *)prail_list, (sizeof(struct ctrl_volt_volt_rail_list)));
/* Execute the voltage change request via PMU RPC. */
status = volt_pmu_rpc_execute(g, &rpc_call);
if (status != 0) {
nvgpu_err(g,
"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
return -EINVAL;
}
return 0;
}
int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv)
{
int status = 0;
struct ctrl_volt_volt_rail_list rail_list = { 0 };
rail_list.num_rails = RAIL_COUNT_GV;
rail_list.rails[0].rail_idx = 0;
rail_list.rails[0].voltage_uv = logic_voltage_uv;
status = volt_policy_set_noiseaware_vmin(g, &rail_list);
return status;
}
int nvgpu_volt_get_vmin_tu10x(struct gk20a *g, u32 *vmin_uv)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct voltage_rail *volt_rail = NULL;
int status;
u8 index;
status = nvgpu_volt_rail_boardobj_grp_get_status(g);
if (status != 0) {
nvgpu_err(g, "Vfe_var get status failed");
return status;
}
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
if (volt_rail->vmin_limitu_v != 0U) {
*vmin_uv = volt_rail->vmin_limitu_v;
return status;
}
}
return status;
}
u8 nvgpu_volt_get_vmargin_tu10x(struct gk20a *g)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct voltage_rail *volt_rail = NULL;
u8 index, vmargin_uv;
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj *, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
if (volt_rail->volt_margin_limit_vfe_equ_idx != 255U) {
vmargin_uv = volt_rail->volt_margin_limit_vfe_equ_idx;
return vmargin_uv;
}
}
return 0U;
return volt_rail_get_voltage(g,
(u8)volt_domain, voltage_uv);
}

7
drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,9 @@
#ifndef NVGPU_VOLT_PMU_H
#define NVGPU_VOLT_PMU_H
#define RAIL_COUNT_GP 2
#define RAIL_COUNT_GV 1
u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
#endif /* NVGPU_VOLT_PMU_H */

7
drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
View File

@@ -28,9 +28,6 @@
#include <nvgpu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_policy.h"
static int volt_policy_pmu_data_init_super(struct gk20a *g,
@@ -473,7 +470,7 @@ done:
return status;
}
int volt_policy_pmu_setup(struct gk20a *g)
int nvgpu_volt_policy_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
@@ -493,7 +490,7 @@ int volt_policy_pmu_setup(struct gk20a *g)
return status;
}
int volt_policy_sw_setup(struct gk20a *g)
int nvgpu_volt_policy_sw_setup(struct gk20a *g)
{
int status = 0;
struct boardobjgrp *pboardobjgrp = NULL;

276
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -27,77 +27,10 @@
#include <nvgpu/string.h>
#include <nvgpu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "gp106/bios_gp106.h"
#include "volt.h"
#include "volt_rail.h"
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
switch (volt_domain) {
case CTRL_VOLT_DOMAIN_LOGIC:
return 0;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
switch (volt_domain) {
case CTRL_VOLT_DOMAIN_LOGIC:
return 0;
case CTRL_VOLT_DOMAIN_SRAM:
return 1;
}
break;
}
return CTRL_BOARDOBJ_IDX_INVALID;
}
int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type)
{
int status = 0;
if (operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
if (pvolt_rail->volt_dev_idx_default ==
CTRL_BOARDOBJ_IDX_INVALID) {
pvolt_rail->volt_dev_idx_default = volt_dev_idx;
} else {
status = -EINVAL;
goto exit;
}
} else if (operation_type ==
CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) {
if (pvolt_rail->volt_dev_idx_ipc_vmin ==
CTRL_BOARDOBJ_IDX_INVALID) {
pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx;
/*
* Exit on purpose as we do not want to register
* IPC_VMIN device against the rail to avoid
* setting current voltage instead of
* IPC Vmin voltage.
*/
goto exit;
} else {
status = -EINVAL;
goto exit;
}
} else {
goto exit;
}
status = boardobjgrpmask_bitset(&pvolt_rail->volt_dev_mask.super,
volt_dev_idx);
exit:
if (status != 0) {
nvgpu_err(g, "Failed to register VOLTAGE_DEVICE");
}
return status;
}
static int volt_rail_state_init(struct gk20a *g,
struct voltage_rail *pvolt_rail)
@@ -224,47 +157,6 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
return (struct voltage_rail *)board_obj_ptr;
}
u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 vbios_volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (vbios_volt_domain == 0U) {
return CTRL_VOLT_DOMAIN_LOGIC;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
switch (vbios_volt_domain) {
case 0:
return CTRL_VOLT_DOMAIN_LOGIC;
case 1:
return CTRL_VOLT_DOMAIN_SRAM;
}
break;
}
return CTRL_VOLT_DOMAIN_INVALID;
}
int volt_rail_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
nvgpu_log_info(g, "Done");
return status;
}
static int volt_get_volt_rail_table(struct gk20a *g,
struct voltage_rail_metadata *pvolt_rail_metadata)
{
@@ -302,7 +194,7 @@ static int volt_get_volt_rail_table(struct gk20a *g,
nvgpu_memcpy((u8 *)&entry, entry_ptr,
sizeof(struct vbios_voltage_rail_table_1x_entry));
volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
volt_domain = nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(g,
i);
if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
continue;
@@ -367,7 +259,7 @@ static int volt_get_volt_rail_table(struct gk20a *g,
status = boardobjgrp_objinsert(
&pvolt_rail_metadata->volt_rails.super,
(struct boardobj *)prail, i);
(void *)(struct boardobj *)prail, i);
}
done:
@@ -438,7 +330,7 @@ static int volt_rail_obj_update(struct gk20a *g,
return 0;
}
int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
static int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
{
struct boardobjgrp *pboardobjgrp;
struct boardobjgrpmask *pboardobjgrpmask;
@@ -477,7 +369,7 @@ int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
return 0;
}
int volt_rail_sw_setup(struct gk20a *g)
int nvgpu_volt_rail_sw_setup(struct gk20a *g)
{
int status = 0;
struct boardobjgrp *pboardobjgrp = NULL;
@@ -549,3 +441,161 @@ done:
nvgpu_log_info(g, " done status %x", status);
return status;
}
int nvgpu_volt_rail_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
nvgpu_log_info(g, "Done");
return status;
}
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
u8 vbios_volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (vbios_volt_domain == 0U) {
return CTRL_VOLT_DOMAIN_LOGIC;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
if (vbios_volt_domain == 0U) {
return CTRL_VOLT_DOMAIN_LOGIC;
} else if (vbios_volt_domain == 1U) {
return CTRL_VOLT_DOMAIN_SRAM;
} else {
nvgpu_info(g, "Split Rail has invalid entry");
}
break;
default:
nvgpu_info(g, "Volt domain is invalid");
break;
}
return CTRL_VOLT_DOMAIN_INVALID;
}
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
{
switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
return 0U;
}
break;
case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) {
return 0U;
} else if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) {
return 1U;
} else {
nvgpu_info(g, "Split Rail has invalid entry");
}
break;
default:
nvgpu_info(g, "Boardobj IDX is invalid");
break;
}
return CTRL_BOARDOBJ_IDX_INVALID;
}
int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type)
{
int status = 0;
if (operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
if (pvolt_rail->volt_dev_idx_default ==
CTRL_BOARDOBJ_IDX_INVALID) {
pvolt_rail->volt_dev_idx_default = volt_dev_idx;
} else {
status = -EINVAL;
goto exit;
}
} else if (operation_type ==
CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) {
if (pvolt_rail->volt_dev_idx_ipc_vmin ==
CTRL_BOARDOBJ_IDX_INVALID) {
pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx;
/*
* Exit on purpose as we do not want to register
* IPC_VMIN device against the rail to avoid
* setting current voltage instead of
* IPC Vmin voltage.
*/
goto exit;
} else {
status = -EINVAL;
goto exit;
}
} else {
goto exit;
}
status = boardobjgrpmask_bitset(&pvolt_rail->volt_dev_mask.super,
volt_dev_idx);
exit:
if (status != 0) {
nvgpu_err(g, "Failed to register VOLTAGE_DEVICE");
}
return status;
}
int nvgpu_volt_get_vmin_ps35(struct gk20a *g, u32 *vmin_uv)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct voltage_rail *volt_rail = NULL;
int status;
u8 index;
status = nvgpu_volt_rail_boardobj_grp_get_status(g);
if (status != 0) {
nvgpu_err(g, "Vfe_var get status failed");
return status;
}
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
if (volt_rail->vmin_limitu_v != 0U) {
*vmin_uv = volt_rail->vmin_limitu_v;
return status;
}
}
return status;
}
u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct voltage_rail *volt_rail = NULL;
u8 index, vmargin_uv;
pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj *, pboardobj, index) {
volt_rail = (struct voltage_rail *)(void *)pboardobj;
if (volt_rail->volt_margin_limit_vfe_equ_idx != 255U) {
vmargin_uv = volt_rail->volt_margin_limit_vfe_equ_idx;
return vmargin_uv;
}
}
return 0U;
}

42
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h
View File

@@ -27,49 +27,7 @@
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU
#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
(boardobjgrp_idxisvalid( \
&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
(!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
/*!
* extends boardobj providing attributes common to all voltage_rails.
*/
struct voltage_rail {
struct boardobj super;
u32 boot_voltage_uv;
u8 rel_limit_vfe_equ_idx;
u8 alt_rel_limit_vfe_equ_idx;
u8 ov_limit_vfe_equ_idx;
u8 pwr_equ_idx;
u8 volt_scale_exp_pwr_equ_idx;
u8 volt_dev_idx_default;
u8 volt_dev_idx_ipc_vmin;
u8 boot_volt_vfe_equ_idx;
u8 vmin_limit_vfe_equ_idx;
u8 volt_margin_limit_vfe_equ_idx;
u32 volt_margin_limit_vfe_equ_mon_handle;
u32 rel_limit_vfe_equ_mon_handle;
u32 alt_rel_limit_vfe_equ_mon_handle;
u32 ov_limit_vfe_equ_mon_handle;
struct boardobjgrpmask_e32 volt_dev_mask;
s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u32 vmin_limitu_v;
};
u8 volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
#endif /* NVGPU_VOLT_RAIL_H */

9
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1127,15 +1127,6 @@ struct gpu_ops {
struct boardobjgrp *pboardobjgrp,
struct boardobjgrp_pmu_cmd *cmd);
} boardobj;
struct {
int (*volt_set_voltage)(struct gk20a *g,
u32 logic_voltage_uv, u32 sram_voltage_uv);
int (*volt_get_voltage)(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int (*volt_send_load_cmd_to_pmu)(struct gk20a *g);
int (*volt_get_vmin)(struct gk20a *g, u32 *vmin_uv);
u8 (*volt_get_vmargin)(struct gk20a *g);
} volt;
struct {
u32 (*get_vbios_clk_domain)(u32 vbios_domain);
int (*clk_avfs_get_vin_cal_data)(struct gk20a *g,

73
drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h
View File

@@ -27,6 +27,18 @@
#include <nvgpu/boardobjgrp_e32.h>
struct gk20a;
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
(boardobjgrp_idxisvalid( \
&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
(!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
/*!
* metadata of voltage rail functionality.
@@ -54,34 +66,47 @@ struct obj_volt {
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
struct voltage_rail {
struct boardobj super;
u32 boot_voltage_uv;
u8 rel_limit_vfe_equ_idx;
u8 alt_rel_limit_vfe_equ_idx;
u8 ov_limit_vfe_equ_idx;
u8 pwr_equ_idx;
u8 volt_scale_exp_pwr_equ_idx;
u8 volt_dev_idx_default;
u8 volt_dev_idx_ipc_vmin;
u8 boot_volt_vfe_equ_idx;
u8 vmin_limit_vfe_equ_idx;
u8 volt_margin_limit_vfe_equ_idx;
u32 volt_margin_limit_vfe_equ_mon_handle;
u32 rel_limit_vfe_equ_mon_handle;
u32 alt_rel_limit_vfe_equ_mon_handle;
u32 ov_limit_vfe_equ_mon_handle;
struct boardobjgrpmask_e32 volt_dev_mask;
s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
u32 vmin_limitu_v;
};
int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
int nvgpu_volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g);
int nvgpu_volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g);
int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
u32 sram_voltage_uv);
int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
u8 volt_domain, u32 *pvoltage_uv);
int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g);
int nvgpu_volt_dev_sw_setup(struct gk20a *g);
int nvgpu_volt_dev_pmu_setup(struct gk20a *g);
int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
int nvgpu_volt_policy_sw_setup(struct gk20a *g);
int nvgpu_volt_policy_pmu_setup(struct gk20a *g);
int volt_dev_sw_setup(struct gk20a *g);
int volt_dev_pmu_setup(struct gk20a *g);
int volt_rail_sw_setup(struct gk20a *g);
int volt_rail_pmu_setup(struct gk20a *g);
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int volt_policy_sw_setup(struct gk20a *g);
int volt_policy_pmu_setup(struct gk20a *g);
int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g);
int nvgpu_volt_get_vmin_tu10x(struct gk20a *g, u32 *vmin_uv);
u8 nvgpu_volt_get_vmargin_tu10x(struct gk20a *g);
int nvgpu_volt_rail_sw_setup(struct gk20a *g);
int nvgpu_volt_rail_pmu_setup(struct gk20a *g);
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int nvgpu_volt_get_vmin_ps35(struct gk20a *g, u32 *vmin_uv);
u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g);
int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal
(struct gk20a *g, u8 vbios_volt_domain);
#endif /* NVGPU_PMU_VOLT_H */

12
drivers/gpu/nvgpu/os/linux/debug_volt.c
View File

@@ -18,7 +18,6 @@
#include "os_linux.h"
#include <nvgpu/pmu/volt.h>
#include <common/pmu/volt/volt_rail.h>
static int get_curr_voltage(void *data, u64 *val)
{
@@ -26,11 +25,7 @@ static int get_curr_voltage(void *data, u64 *val)
u32 readval;
int err;
if (!g->ops.pmu_ver.volt.volt_get_voltage)
return -EINVAL;
err = g->ops.pmu_ver.volt.volt_get_voltage(g,
CTRL_VOLT_DOMAIN_LOGIC, &readval);
err = nvgpu_volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &readval);
if (!err)
*val = readval;
@@ -44,10 +39,7 @@ static int get_min_voltage(void *data, u64 *val)
u32 readval;
int err;
if (!g->ops.pmu_ver.volt.volt_get_vmin)
return -EINVAL;
err = g->ops.pmu_ver.volt.volt_get_vmin(g, &readval);
err = nvgpu_volt_get_vmin_ps35(g, &readval);
if (!err)
*val = readval;

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1395,10 +1395,10 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g,
nvgpu_speculation_barrier();
switch (args->which) {
case NVGPU_GPU_VOLTAGE_CORE:
err = volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &args->voltage);
err = nvgpu_volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &args->voltage);
break;
case NVGPU_GPU_VOLTAGE_SRAM:
err = volt_get_voltage(g, CTRL_VOLT_DOMAIN_SRAM, &args->voltage);
err = nvgpu_volt_get_voltage(g, CTRL_VOLT_DOMAIN_SRAM, &args->voltage);
break;
case NVGPU_GPU_VOLTAGE_BUS:
err = pmgr_pwr_devices_get_voltage(g, &args->voltage);