diff --git a/drivers/gpu/nvgpu/common/fifo/submit.c b/drivers/gpu/nvgpu/common/fifo/submit.c
index 1e9a5adb6..a6d0888b6 100644
--- a/drivers/gpu/nvgpu/common/fifo/submit.c
+++ b/drivers/gpu/nvgpu/common/fifo/submit.c
@@ -151,9 +151,8 @@ static int nvgpu_submit_prepare_syncs(struct nvgpu_channel *c,
 
 	if (flag_fence_get) {
 		err = nvgpu_channel_sync_incr_user(c->sync,
-			wait_fence_fd, job->incr_cmd,
-			job->post_fence, need_wfi, need_sync_fence,
-			register_irq);
+			job->incr_cmd, job->post_fence, need_wfi,
+			need_sync_fence, register_irq);
 	} else {
 		err = nvgpu_channel_sync_incr(c->sync,
 			job->incr_cmd, job->post_fence, need_sync_fence,
diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync.c b/drivers/gpu/nvgpu/common/sync/channel_sync.c
index a912607a1..c773f7469 100644
--- a/drivers/gpu/nvgpu/common/sync/channel_sync.c
+++ b/drivers/gpu/nvgpu/common/sync/channel_sync.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Channel Synchronization Abstraction
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -71,12 +71,11 @@ int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
 }
 
 int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
-	int wait_fence_fd, struct priv_cmd_entry *entry,
-	struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
-	bool register_irq)
+	struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence, bool wfi,
+	bool need_sync_fence, bool register_irq)
 {
-	return s->ops->incr_user(s, wait_fence_fd, entry, fence, wfi,
-		need_sync_fence, register_irq);
+	return s->ops->incr_user(s, entry, fence, wfi, need_sync_fence,
+			register_irq);
 }
 
 void nvgpu_channel_sync_set_min_eq_max(struct nvgpu_channel_sync *s)
diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_priv.h b/drivers/gpu/nvgpu/common/sync/channel_sync_priv.h
index f46d6c800..69f8bbcfc 100644
--- a/drivers/gpu/nvgpu/common/sync/channel_sync_priv.h
+++ b/drivers/gpu/nvgpu/common/sync/channel_sync_priv.h
@@ -1,8 +1,7 @@
 /*
- *
  * Nvgpu Channel Synchronization Abstraction
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -67,7 +66,6 @@ struct nvgpu_channel_sync_ops {
 		    bool register_irq);
 
 	int (*incr_user)(struct nvgpu_channel_sync *s,
-			 int wait_fence_fd,
 			 struct priv_cmd_entry *entry,
 			 struct nvgpu_fence_type *fence,
 			 bool wfi,
diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c
index 4d3b670ec..ad8e6df0a 100644
--- a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c
+++ b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Channel Synchronization Abstraction
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -243,7 +243,6 @@ static int channel_sync_semaphore_incr(
 
 static int channel_sync_semaphore_incr_user(
 		struct nvgpu_channel_sync *s,
-		int wait_fence_fd,
 		struct priv_cmd_entry *entry,
 		struct nvgpu_fence_type *fence,
 		bool wfi,
diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
index 463b8218f..807e43457 100644
--- a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
+++ b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
@@ -263,7 +263,6 @@ static int channel_sync_syncpt_incr(struct nvgpu_channel_sync *s,
 }
 
 static int channel_sync_syncpt_incr_user(struct nvgpu_channel_sync *s,
-				   int wait_fence_fd,
 				   struct priv_cmd_entry *entry,
 				   struct nvgpu_fence_type *fence,
 				   bool wfi,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
index 43feb2637..2be1e780d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
@@ -1,8 +1,7 @@
 /*
- *
  * Nvgpu Channel Synchronization Abstraction
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -65,9 +64,8 @@ int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
  *  - a nvgpu_fence_type that signals when the incr has happened.
  */
 int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
-	int wait_fence_fd, struct priv_cmd_entry *entry,
-	struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
-	bool register_irq);
+	struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence, bool wfi,
+	bool need_sync_fence, bool register_irq);
 /*
  * Reset the channel syncpoint/semaphore. Syncpoint increments generally
  * wrap around the range of integer values. Current max value encompasses