diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index d6bd32758..96812e8d8 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -634,17 +634,15 @@ static int gr_reset_engine(struct gk20a *g)
 	}
 
 	/*
-	 * Do not reset PERFMON and BLG when MIG is enabled as PERFMON is a
-	 * global engine which is shared by all syspipes. Individual PERF
-	 * counters can be reset during gr syspipe reset.
+	 * TODO: Do not reset PERFMON in gr_reset_engine() as PERFMON is a
+	 * global engine which is shared by all contexts/syspipes.
+	 * Individual PERF counters can be reset during gr syspipe reset.
 	 */
-	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
-		err = nvgpu_mc_reset_units(g,
-			NVGPU_UNIT_PERFMON | NVGPU_UNIT_BLG);
-		if (err != 0) {
-			nvgpu_log_info(g, "PERMON | BLG unit reset failed");
-			return err;
-		}
+	err = nvgpu_mc_reset_units(g,
+		NVGPU_UNIT_PERFMON | NVGPU_UNIT_BLG);
+	if (err != 0) {
+		nvgpu_log_info(g, "PERMON | BLG unit reset failed");
+		return err;
 	}
 
 	nvgpu_log(g, gpu_dbg_gr, "done");
diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index b5b5ee014..afab3d57d 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -494,6 +494,19 @@ static int nvgpu_gr_obj_ctx_init_hw_state(struct gk20a *g,
 	/* load ctx init */
 	nvgpu_log_info(g, "begin: netlist: sw_ctx_load: register writes");
 	for (i = 0U; i < sw_ctx_load->count; i++) {
+#ifdef CONFIG_NVGPU_MIG
+		if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+				(g->ops.gr.init.is_allowed_reg != NULL) &&
+				(!(g->ops.gr.init.is_allowed_reg(g,
+					sw_ctx_load->l[i].addr)))) {
+			nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+				"(MIG) Skip graphics ctx load reg "
+					"index[%u] addr[%x] value[%x] ",
+				i, sw_ctx_load->l[i].addr,
+				sw_ctx_load->l[i].value);
+			continue;
+		}
+#endif
 		nvgpu_writel(g, sw_ctx_load->l[i].addr,
 			     sw_ctx_load->l[i].value);
 	}
diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index f1d48ea4a..3e54f2b8f 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -163,12 +163,14 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 	g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
 
 	nvgpu_log(g, gpu_dbg_mig,
-		"[Physical device] gpu_instance_id[%u] gr_instance_id[%u] "
+		"[%s] gpu_instance_id[%u] gr_instance_id[%u] "
 			"gr_syspipe_id[%u] max_gpc_count[%u] num_gpc[%u] "
 			"gr_engine_id[%u] max_veid_count_per_tsg[%u] "
 			"veid_start_offset[%u] is_memory_partition_support[%d] "
 			"num_lce[%u] max_fbps_count[%u] num_fbp[%u] "
 			"fbp_en_mask [0x%x] ",
+		(nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG) ?
+			"MIG_Physical" : "Physical"),
 		gpu_instance->gpu_instance_id,
 		gr_syspipe->gr_instance_id,
 		gr_syspipe->gr_syspipe_id,
diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c
index 2076c2d44..4f6e0a7c5 100644
--- a/drivers/gpu/nvgpu/common/netlist/netlist.c
+++ b/drivers/gpu/nvgpu/common/netlist/netlist.c
@@ -317,11 +317,6 @@ static bool nvgpu_netlist_handle_debugger_region_id(struct gk20a *g,
 		err = nvgpu_netlist_alloc_load_aiv_list(g,
 			src, size, &netlist_vars->ctxsw_regs.pm_tpc);
 		break;
-	case NETLIST_REGIONID_CTXREG_PMPPC:
-		nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PMPPC");
-		err = nvgpu_netlist_alloc_load_aiv_list(g,
-			src, size, &netlist_vars->ctxsw_regs.pm_ppc);
-		break;
 	case NETLIST_REGIONID_NVPERF_CTXREG_SYS:
 		nvgpu_log_info(g, "NETLIST_REGIONID_NVPERF_CTXREG_SYS");
 		err = nvgpu_netlist_alloc_load_aiv_list(g,
@@ -501,6 +496,11 @@ static bool nvgpu_netlist_handle_debugger_region_id(struct gk20a *g,
 			err = nvgpu_netlist_alloc_load_aiv_list(g,
 				src, size, &netlist_vars->ctxsw_regs.ppc);
 			break;
+		case NETLIST_REGIONID_CTXREG_PMPPC:
+			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PMPPC");
+			err = nvgpu_netlist_alloc_load_aiv_list(g,
+				src, size, &netlist_vars->ctxsw_regs.pm_ppc);
+			break;
 		case NETLIST_REGIONID_CTXREG_PMROP:
 			nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PMROP");
 			err = nvgpu_netlist_alloc_load_aiv_list(g,
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
index 5f2f439e0..982d92f8f 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,6 +31,13 @@ struct gk20a;
 struct nvgpu_gr_ctx;
 struct nvgpu_gr_config;
 
+#ifdef CONFIG_NVGPU_MIG
+struct nvgpu_gr_gfx_reg_range {
+	u32 start_addr;
+	u32 end_addr;
+};
+#endif
+
 void ga10b_gr_init_override_context_reset(struct gk20a *g);
 void ga10b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable);
 void ga10b_gr_init_auto_go_idle(struct gk20a *g, bool enable);
@@ -69,5 +76,7 @@ int ga10b_gr_init_wait_idle(struct gk20a *g);
 void ga10b_gr_init_eng_config(struct gk20a *g);
 int ga10b_gr_init_reset_gpcs(struct gk20a *g);
 int ga10b_gr_init_wait_empty(struct gk20a *g);
-
+#ifdef CONFIG_NVGPU_MIG
+bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr);
+#endif
 #endif /* NVGPU_GR_INIT_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
index 1d614b9ae..d0d7268f5 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b_fusa.c
@@ -516,3 +516,101 @@ int ga10b_gr_init_wait_empty(struct gk20a *g)
 
 	return -EAGAIN;
 }
+
+#ifdef CONFIG_NVGPU_MIG
+bool ga10b_gr_init_is_allowed_reg(struct gk20a *g, u32 addr)
+{
+	struct nvgpu_gr_gfx_reg_range gfx_range[] = {
+		/* start_addr, end_addr */
+		{ 0x00405800 /* gr_pri_ds_debug */,
+			0x00405864 /* gr_pri_ds_cg1 */ },
+		{ 0x00405900 /* gr_pri_pdb - start */,
+			0x004059ff /* gr_pri_pdb - end */ },
+		{ 0x00405a00 /* gr_pri_ssync - start */,
+			0x00405aff /* gr_pri_ssync - end */ },
+		{ 0x00406000 /* gr_pri_pd_cg */,
+			0x00406518
+			/* gr_pri_pd_output_batch_stall__priv_level_mask */ },
+		{ 0x00407800 /* gr_pri_pd_rstr2d - start */,
+			0x00407fff /* gr_pri_pd_rstr2d - end */ },
+		{ 0x00408000 /* gr_pri_pd_scc - start */,
+			0x004087ff /* gr_pri_pd_scc - end */ },
+		/*
+		 * ga10b doesn't have bes, but for some ampere GPU,
+		 * the following pes reg_range is valid.
+		 * For ga10b, the following bes range is unused.
+		 */
+		{ 0x00408800 /* gr_pri_bes - start */,
+			0x004089ff /* gr_pri_bes_rdm - end */ },
+		{ 0x00408a24 /* gr_pri_bes_becs_cg1 - start */,
+			0x00408a24 /* gr_pri_bes_becs_cg1 - end */ },
+		{ 0x00408a80 /* gr_pri_bes_crop_cg - start */,
+			0x00408a84 /* gr_pri_bes_crop_cg1 - end */ },
+		/*
+		 * For ga10b, end_addr is 0x00418ea7.
+		 * but for some ampere GPU, end_address is 0x00418eff.
+		 * So maximum possible end_addr is 0x00418eff.
+		 * For ga10b, range 0x00418ea7 - 0x00418eff is unused.
+		 */
+		{ 0x00418000 /* gr_pri_gpcs_swdx_dss_debug */,
+			0x00418eff
+				/* gr_pri_gpcs_swdx_tc_beta_cb_size */ },
+
+		{ 0x00418380 /* gr_pri_gpcs_rasterarb - start */,
+			0x004183ff /* gr_pri_gpcs_rasterarb - end */ },
+		{ 0x00418400 /* gr_pri_gpcs_prop - start */,
+			0x004185ff /* gr_pri_gpcs_prop - end */ },
+		{ 0x00418600 /* gr_pri_gpcs_frstr - start */,
+			0x0041867f /* gr_pri_gpcs_frstr - end */ },
+		{ 0x00418680 /* gr_pri_gpcs_widcilp - start */,
+			0x004186ff /* gr_pri_gpcs_widcilp - end */ },
+		{ 0x00418700 /* gr_pri_gpcs_tc - start */,
+			0x004187ff /* gr_pri_gpcs_tc - end */ },
+		{ 0x00418800 /* gr_pri_gpcs_setup - start */,
+			0x0041887f /* gr_pri_gpcs_setup - end */ },
+		{ 0x004188c0 /* gr_pri_gpcs_zcull_zcram_index */,
+			0x00418af8 /* gr_pri_gpcs_zcull_zcsstatus_7 */ },
+		{ 0x00418b00 /* gr_pri_gpcs_crstr - start */,
+			0x00418bff /* gr_pri_gpcs_crstr - end */ },
+		{ 0x00418d00 /* gr_pri_gpcs_gpm_rpt - start */,
+			0x00418d7f /* gr_pri_gpcs_gpm_rpt - end */ },
+		{ 0x00418f00 /* gr_pri_gpcs_wdxps - start */,
+			0x00418fff /* gr_pri_gpcs_wdxps - end */ },
+		{ 0x00419804 /* gr_pri_gpcs_tpcs_pe_blkcg_cg */,
+			0x00419900
+			/* gr_pri_gpcs_tpcs_pe_blk_activity_weigts_c */ },
+		{ 0x0041be00 /* gr_pri_gpcs_ppcs */,
+			0x0041bfff /* gr_pri_gpcs_ppcs_wwdx - end */ },
+	};
+
+	u32 gfx_range_size = (sizeof(gfx_range) /
+		sizeof(struct nvgpu_gr_gfx_reg_range));
+	u32 index;
+
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_log(g, gpu_dbg_gr,
+			"Allowed reg addr[%x] ", addr);
+		return true;
+	}
+	/*
+	 * Capture whether the ctx_load address is compute subunit or not.
+	 */
+	for (index = 0U; index < gfx_range_size; index++) {
+		if ((addr >= gfx_range[index].start_addr) &&
+				(addr <= gfx_range[index].end_addr)) {
+			nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+				"(MIG) Skip graphics reg index[%u] "
+					"addr[%x] start_addr[%x] end_addr[%x] ",
+				index, addr,
+				gfx_range[index].start_addr,
+				gfx_range[index].end_addr);
+			return false;
+		}
+	}
+
+	nvgpu_log(g, gpu_dbg_gr, "Allowed compute reg addr[%x] ",
+		addr);
+
+	return true;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c
index dd58f0c0d..787c2428f 100644
--- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -364,18 +364,27 @@ void gm20b_gr_init_load_method_init(struct gk20a *g,
 {
 	u32 i;
 	u32 last_method_data = 0U;
+	u32 class_num = 0U;
 
-	if (sw_method_init->count != 0U) {
-		nvgpu_writel(g, gr_pri_mme_shadow_ram_data_r(),
-			     sw_method_init->l[0U].value);
-		nvgpu_writel(g, gr_pri_mme_shadow_ram_index_r(),
-			     gr_pri_mme_shadow_ram_index_write_trigger_f() |
-			     sw_method_init->l[0U].addr);
-		last_method_data = sw_method_init->l[0U].value;
-	}
-
-	for (i = 1U; i < sw_method_init->count; i++) {
-		if (sw_method_init->l[i].value != last_method_data) {
+	for (i = 0U; i < sw_method_init->count; i++) {
+		class_num = gr_pri_mme_shadow_ram_index_nvclass_v(
+			sw_method_init->l[i].addr);
+#ifdef CONFIG_NVGPU_MIG
+		if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+				(!g->ops.gpu_class.is_valid_compute(
+					class_num))) {
+			nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+				"(MIG) Skip graphics sw method index[%u] "
+					"addr[%x] value[%x] class_num[%x] ",
+				i, sw_method_init->l[i].addr,
+				sw_method_init->l[i].value,
+				class_num);
+			continue;
+		}
+#endif
+		if ((i == 0U) ||
+				(sw_method_init->l[i].value !=
+					last_method_data)) {
 			nvgpu_writel(g, gr_pri_mme_shadow_ram_data_r(),
 				sw_method_init->l[i].value);
 			last_method_data = sw_method_init->l[i].value;
@@ -383,6 +392,12 @@ void gm20b_gr_init_load_method_init(struct gk20a *g,
 		nvgpu_writel(g, gr_pri_mme_shadow_ram_index_r(),
 			gr_pri_mme_shadow_ram_index_write_trigger_f() |
 			sw_method_init->l[i].addr);
+		nvgpu_log(g, gpu_dbg_gr,
+			"Allowed graphics sw method index[%u] "
+				"addr[%x] value[%x] class_num[%x] ",
+			i, sw_method_init->l[i].addr,
+			sw_method_init->l[i].value,
+			class_num);
 	}
 }
 
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
index b14e0f88b..70e076c9f 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
@@ -790,16 +790,20 @@ void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g)
 	nvgpu_writel(g, gr_memfmt_hww_esr_r(),
 		     gr_memfmt_hww_esr_en_enable_f() |
 		     gr_memfmt_hww_esr_reset_active_f());
-	nvgpu_writel(g, gr_pd_hww_esr_r(),
-		     gr_pd_hww_esr_en_enable_f() |
-		     gr_pd_hww_esr_reset_active_f());
-	nvgpu_writel(g, gr_scc_hww_esr_r(),
-		     gr_scc_hww_esr_en_enable_f() |
-		     gr_scc_hww_esr_reset_active_f());
-	nvgpu_writel(g, gr_ds_hww_esr_r(),
-		     gr_ds_hww_esr_en_enabled_f() |
-		     gr_ds_hww_esr_reset_task_f());
+	/*
+	 * PD, SCC, DS, SSYNC - SYS Graphics Units.
+	 * Accessible only in legacy mode (graphics+compute).
+	 */
 	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		nvgpu_writel(g, gr_pd_hww_esr_r(),
+				 gr_pd_hww_esr_en_enable_f() |
+				 gr_pd_hww_esr_reset_active_f());
+		nvgpu_writel(g, gr_scc_hww_esr_r(),
+				 gr_scc_hww_esr_en_enable_f() |
+				 gr_scc_hww_esr_reset_active_f());
+		nvgpu_writel(g, gr_ds_hww_esr_r(),
+				 gr_ds_hww_esr_en_enabled_f() |
+				 gr_ds_hww_esr_reset_task_f());
 		nvgpu_writel(g, gr_ssync_hww_esr_r(),
 		        gr_ssync_hww_esr_en_enable_f() |
 		        gr_ssync_hww_esr_reset_active_f());
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
index 4736b2221..b0e69aea3 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
@@ -768,10 +768,14 @@ int ga10b_grmgr_init_gr_manager(struct gk20a *g)
 
 	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG) ||
 			(g->mig.gpc_count < 2U)) {
-		nvgpu_set_enabled(g, NVGPU_SUPPORT_MIG, false);
-		/* Fall back to non MIG gr manager init */
+		/*
+		 * Fall back to 1 GPU instance.
+		 * It can be Physical/legacy or MIG mode based NVGPU_SUPPORT_MIG.
+		 */
 		nvgpu_log(g, gpu_dbg_mig,
-			"legacy mode boot[non MIG]");
+			"Fall back to 1 GPU instance - mode[%s]",
+			(nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG) ?
+				"MIG_Physical" : "Physical"));
 		return 0;
 	}
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 005a4bca9..3e3adb5fa 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -661,6 +661,9 @@ static const struct gops_gr_init ga100_ops_gr_init = {
 	.get_ctx_pagepool_size = gp10b_gr_init_get_ctx_pagepool_size,
 	.get_ctx_betacb_size = ga100_gr_init_get_ctx_betacb_size,
 	.commit_ctxsw_spill = gv11b_gr_init_commit_ctxsw_spill,
+#ifdef CONFIG_NVGPU_MIG
+	.is_allowed_reg = ga10b_gr_init_is_allowed_reg,
+#endif
 #endif /* CONFIG_NVGPU_GFXP */
 };
 
@@ -1314,7 +1317,6 @@ static const struct gops_clk ga100_ops_clk = {
 	.get_cntr_xbarclk_source = ga100_clk_get_cntr_xbarclk_source,
 	.get_cntr_sysclk_source = ga100_clk_get_cntr_sysclk_source,
 #endif
-	.change_host_clk_source = tu104_change_host_clk_source,
 	.perf_pmu_vfe_load = nvgpu_pmu_perf_load,
 	.clk_mon_init_domains = nvgpu_pmu_clk_mon_init_domains,
 };
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index 0a55a65d2..76ce838f7 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -635,6 +635,9 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
 	.get_ctx_pagepool_size = gp10b_gr_init_get_ctx_pagepool_size,
 	.get_ctx_betacb_size = ga10b_gr_init_get_ctx_betacb_size,
 	.commit_ctxsw_spill = gv11b_gr_init_commit_ctxsw_spill,
+#ifdef CONFIG_NVGPU_MIG
+	.is_allowed_reg = ga10b_gr_init_is_allowed_reg,
+#endif
 #endif /* CONFIG_NVGPU_GFXP */
 };
 
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
index 9896335f9..216821705 100644
--- a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
@@ -447,6 +447,19 @@ void ga100_slcg_gr_load_gating_prod(struct gk20a *g,
 			u32 reg = ga100_slcg_gr[i].addr;
 			u32 val = prod ? ga100_slcg_gr[i].prod :
 					 ga100_slcg_gr[i].disable;
+#ifdef CONFIG_NVGPU_MIG
+			if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+					(g->ops.gr.init.is_allowed_reg
+						!= NULL) &&
+					(!(g->ops.gr.init.is_allowed_reg(g,
+						reg)))) {
+				nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+					"(MIG) Skip slcg graphics gating reg "
+						"index[%u] addr[%x] value[%x] ",
+					i, reg, val);
+				continue;
+			}
+#endif
 			nvgpu_writel(g, reg, val);
 		}
 	}
@@ -805,6 +818,19 @@ void ga100_blcg_gr_load_gating_prod(struct gk20a *g,
 			u32 reg = ga100_blcg_gr[i].addr;
 			u32 val = prod ? ga100_blcg_gr[i].prod :
 					 ga100_blcg_gr[i].disable;
+#ifdef CONFIG_NVGPU_MIG
+			if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+					(g->ops.gr.init.is_allowed_reg
+						!= NULL) &&
+					(!(g->ops.gr.init.is_allowed_reg(g,
+						reg)))) {
+				nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+					"(MIG) Skip blcg graphics gating reg "
+						"index[%u] addr[%x] value[%x] ",
+					i, reg, val);
+				continue;
+			}
+#endif
 			nvgpu_writel(g, reg, val);
 		}
 	}
diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
index f06ffa557..5e5006bed 100644
--- a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
+++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
@@ -475,6 +475,19 @@ void ga10b_slcg_gr_load_gating_prod(struct gk20a *g,
 			u32 reg = ga10b_slcg_gr[i].addr;
 			u32 val = prod ? ga10b_slcg_gr[i].prod :
 					 ga10b_slcg_gr[i].disable;
+#ifdef CONFIG_NVGPU_MIG
+			if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+					(g->ops.gr.init.is_allowed_reg
+						!= NULL) &&
+					(!(g->ops.gr.init.is_allowed_reg(g,
+						reg)))) {
+				nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+					"(MIG) Skip slcg graphics gating reg "
+						"index[%u] addr[%x] value[%x] ",
+				i, reg, val);
+				continue;
+			}
+#endif
 			nvgpu_writel(g, reg, val);
 		}
 	}
@@ -995,6 +1008,19 @@ void ga10b_blcg_gr_load_gating_prod(struct gk20a *g,
 			u32 reg = ga10b_blcg_gr[i].addr;
 			u32 val = prod ? ga10b_blcg_gr[i].prod :
 					 ga10b_blcg_gr[i].disable;
+#ifdef CONFIG_NVGPU_MIG
+			if ((nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) &&
+					(g->ops.gr.init.is_allowed_reg
+						!= NULL) &&
+					(!(g->ops.gr.init.is_allowed_reg(g,
+						reg)))) {
+				nvgpu_log(g, gpu_dbg_mig | gpu_dbg_gr,
+					"(MIG) Skip blcg graphics gating reg "
+						"index[%u] addr[%x] value[%x] ",
+					i, reg, val);
+				continue;
+			}
+#endif
 			nvgpu_writel(g, reg, val);
 		}
 	}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
index 887ad2d18..a8d08bd87 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
@@ -835,6 +835,7 @@ struct gops_gr_init {
 #endif
 	bool (*is_allowed_sw_bundle)(struct gk20a *g,
 			u32 bundle_addr, u32 bundle_value, int *context);
+	bool (*is_allowed_reg)(struct gk20a *g, u32 addr);
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
 	void (*auto_go_idle)(struct gk20a *g, bool enable);
 	void (*eng_config)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_instances.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_instances.h
index 7ebc60f73..c8a8fcd01 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_instances.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_instances.h
@@ -119,6 +119,26 @@
 #define nvgpu_gr_exec_for_all_instances(g, func)	(func)
 #endif
 
+#ifdef CONFIG_NVGPU_MIG
+#define nvgpu_gr_exec_with_ret_for_all_instances(g, func) \
+	({ \
+		int err = 0; \
+		if (nvgpu_grmgr_is_multi_gr_enabled(g)) { \
+			nvgpu_grmgr_config_gr_remap_window(g, \
+				NVGPU_MIG_INVALID_GR_SYSPIPE_ID, false); \
+			g->mig.cur_gr_instance = 0; \
+			err = (func); \
+			nvgpu_grmgr_config_gr_remap_window(g, \
+			 NVGPU_MIG_INVALID_GR_SYSPIPE_ID, true); \
+		} else { \
+			err = (func); \
+		} \
+		err; \
+	})
+#else
+#define nvgpu_gr_exec_with_ret_for_all_instances(g, func)	(func)
+#endif
+
 #ifdef CONFIG_NVGPU_MIG
 #define nvgpu_gr_exec_for_instance(g, gr_instance_id, func) \
 	({ \
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
index d1e5f374c..f7ac1dce9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
@@ -440,6 +440,7 @@
 		(nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
 #define gr_pri_mme_shadow_ram_index_nvclass_f(v)      ((U32(v) & 0xffffU) << 0U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
 #define gr_pri_mme_shadow_ram_index_method_address_f(v)\
 				((U32(v) & 0xfffU) << 16U)
 #define gr_pri_mme_shadow_ram_index_fepipe_f(v)         ((U32(v) & 0x1U) << 29U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
index eff9bc3be..1a5596a30 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
@@ -436,6 +436,7 @@
 #define gr_fe_tpc_fs_r(i)\
 		(nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
 #define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
 #define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
 #define gr_mme_hww_esr_r()                                         (0x00404490U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index d76a89bff..f4dd30112 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -205,6 +205,8 @@
 #define gr_fe_object_table_nvclass_v(r)                  (((r) >> 0U) & 0xffffU)
 #define gr_fe_tpc_fs_r()                                           (0x004041c4U)
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
+							    /* NEEDS_IP_AUDIT */
 #define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
 #define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
 #define gr_mme_hww_esr_r()                                         (0x00404490U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index 66251b46d..8cb7c8db7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -270,6 +270,8 @@
 #define gr_fe_object_table_nvclass_v(r)                  (((r) >> 0U) & 0xffffU)
 #define gr_fe_tpc_fs_r()                                           (0x004041c4U)
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
+							    /* NEEDS_IP_AUDIT */
 #define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
 #define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
 #define gr_mme_hww_esr_r()                                         (0x00404490U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 118536090..b6552abd1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -595,6 +595,7 @@
 #define gr_fe_tpc_pesmask_mask_m()                          (U32(0xffffU) << 0U)
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
 #define gr_pri_mme_shadow_ram_index_nvclass_f(v)      ((U32(v) & 0xffffU) << 0U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
 #define gr_pri_mme_shadow_ram_index_method_address_f(v)\
 				((U32(v) & 0xfffU) << 16U)
 #define gr_pri_mme_shadow_ram_index_fepipe_f(v)         ((U32(v) & 0x1U) << 29U)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
index 598dc81b8..1d698e79d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
@@ -366,6 +366,7 @@
 #define gr_fe_tpc_fs_r(i)\
 		(nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_pri_mme_shadow_ram_index_r()                            (0x00404488U)
+#define gr_pri_mme_shadow_ram_index_nvclass_v(r)         (((r) >> 0U) & 0xffffU)
 #define gr_pri_mme_shadow_ram_index_write_trigger_f()              (0x80000000U)
 #define gr_pri_mme_shadow_ram_data_r()                             (0x0040448cU)
 #define gr_mme_hww_esr_r()                                         (0x00404490U)
diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c
index 1442f260c..1c5efb5b8 100644
--- a/drivers/gpu/nvgpu/os/linux/module.c
+++ b/drivers/gpu/nvgpu/os/linux/module.c
@@ -456,7 +456,9 @@ int gk20a_pm_finalize_poweron(struct device *dev)
 #ifdef CONFIG_NVGPU_DGPU
 	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE) &&
 			nvgpu_platform_is_silicon(g)) {
-		g->ops.clk.change_host_clk_source(g);
+		if (g->ops.clk.change_host_clk_source != NULL) {
+			g->ops.clk.change_host_clk_source(g);
+		}
 		g->ops.xve.devinit_deferred_settings(g);
 	}