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gpu: nvgpu: Update GM20b GPCPLL NA mode settings

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- Updated DFS_COEFF slope/intercept parameters
- Specified VCO control gain
- Increased safe DVFS margin to 10%

Bug 1555318

Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552446
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
This commit is contained in:
Alex Frid
2014-09-30 23:19:50 -07:00
committed by Dan Willemsen
parent f65d2dde97
commit e98ac1867d
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
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@@ -43,7 +43,7 @@
#define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */ #define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */
#define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ #define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */
#define DVFS_SAFE_MARGIN 8 /* 8% */ #define DVFS_SAFE_MARGIN 10 /* 10% */
static unsigned long dvfs_safe_max_freq; static unsigned long dvfs_safe_max_freq;
static struct pll_parms gpc_pll_params = { static struct pll_parms gpc_pll_params = {
@@ -53,9 +53,9 @@ static struct pll_parms gpc_pll_params = {
1, 255, /* M */ 1, 255, /* M */
8, 255, /* N */ 8, 255, /* N */
1, 31, /* PL */ 1, 31, /* PL */
-58700, 86789, /* DFS_COEFF */ -165230, 214007, /* DFS_COEFF */
0, 0, /* ADC char coeff - to be read from fuses */ 0, 0, /* ADC char coeff - to be read from fuses */
0, /* FIXME: vco control data */ 0x7 << 3, /* vco control in NA mode */
}; };
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS