From e9a8fa028edd40a3e1c31b51c8087d52ba13a726 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 14 Apr 2021 14:40:26 +0530 Subject: [PATCH] gpu: nvgpu: disable ssync access when MIG is enabled Disable access to ssync unit when MIG is enabled as ssync is part of GR and not Compute. A runtime check is now added for the below function. gv11b_gr_intr_enable_hww_exceptions The following priv errors are seen. SYS write error: ADR 0x00405a14 WRDAT 0xc0000000 master 0x00000000 [ERR] INFO 0x19400200: (subid 0x00000019 priv_level 0 local_ordering 1) [ERR] CODE 0xbadf1100 Jira NVGPU-6699 Change-Id: I9a08f1b6ab58affdcaa18e8ca314a4a00478a3e5 Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514761 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Lakshmanan M Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c index 343181609..296f4efc7 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c @@ -779,9 +779,11 @@ void gv11b_gr_intr_enable_hww_exceptions(struct gk20a *g) nvgpu_writel(g, gr_ds_hww_esr_r(), gr_ds_hww_esr_en_enabled_f() | gr_ds_hww_esr_reset_task_f()); - nvgpu_writel(g, gr_ssync_hww_esr_r(), - gr_ssync_hww_esr_en_enable_f() | - gr_ssync_hww_esr_reset_active_f()); + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + nvgpu_writel(g, gr_ssync_hww_esr_r(), + gr_ssync_hww_esr_en_enable_f() | + gr_ssync_hww_esr_reset_active_f()); + } nvgpu_writel(g, gr_mme_hww_esr_r(), gr_mme_hww_esr_en_enable_f() | gr_mme_hww_esr_reset_active_f());