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gpu: nvgpu: secure boot HAL update
Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: I343b289f2236fd6a6b0ecf9115367ce19990e7d5 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1151784 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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committed by
Terje Bergstrom
parent
ad24c028db
commit
e9d5e7dfca
@@ -2758,9 +2758,12 @@ static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
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int gk20a_pmu_reset(struct gk20a *g)
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{
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gk20a_reset(g, mc_enable_pwr_enabled_f());
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int err;
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struct pmu_gk20a *pmu = &g->pmu;
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return 0;
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err = pmu_reset(pmu);
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return err;
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}
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void gk20a_init_pmu_ops(struct gpu_ops *gops)
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@@ -2776,6 +2779,12 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
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gops->pmu.pmu_pg_grinit_param = NULL;
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gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
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gops->pmu.dump_secure_fuses = NULL;
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gops->pmu.is_lazy_bootstrap = NULL;
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gops->pmu.is_priv_load = NULL;
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gops->pmu.get_wpr = NULL;
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gops->pmu.alloc_blob_space = NULL;
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gops->pmu.pmu_populate_loader_cfg = NULL;
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gops->pmu.flcn_populate_bl_dmem_desc = NULL;
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gops->pmu.reset = gk20a_pmu_reset;
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}
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