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gpu: nvgpu: fix MISRA rule 14.2 for loops

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MISRA Rule 14.2 requires for loop to be well-formed. A well-formed for
loop has below requirements:
1. first clause can be empty or should assign value to a single loop
counter
2. second clause should exist and use loop counter or loop control flag.
It should not use any variable modified in the loop body.
3. third cluase should only update loop counter and should not use
objects modified in the loop body.

This modifies for loops to process single loop counter. The patch moves
additional initializations before for loop, conditions at loop start
and variable updates at the end of for loop.

Jira NVGPU-855

Change-Id: I93ccf1ac0677ff355364a718d2d953467f1d9d95
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-05-01 09:27:44 -07:00
committed by mobile promotions
parent 4b1d58e3f9
commit e9e9ae9b92
6 changed files with 23 additions and 11 deletions
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4
drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c
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@@ -174,10 +174,11 @@ static int parse_pstate_table_6x(struct gk20a *g,
U32(hdr->clock_entry_count) *
U32(hdr->clock_entry_size);
for (i = 0; i < hdr->base_entry_count; i++, p += entry_size) {
for (i = 0; i < hdr->base_entry_count; i++) {
entry = (struct vbios_pstate_entry_6x *)p;
if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY) {
p += entry_size;
continue;
}
@@ -195,6 +196,7 @@ static int parse_pstate_table_6x(struct gk20a *g,
if (err != 0) {
goto done;
}
p += entry_size;
}
done: