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gpu: nvgpu: Do not touch gr status mask

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GR status disable mask was never set, so driver always disabled all
engines from status rollup.

Change-Id: I500a127be9253294f73d1f42ce89b886471a9117
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719141
This commit is contained in:
Terje Bergstrom
2015-03-18 15:28:23 -07:00
committed by Dan Willemsen
parent 84aae5639e
commit e9f8cb79f1
2 changed files with 0 additions and 6 deletions
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4
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -4214,10 +4214,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF); gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF);
gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF); gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF);
/* ignore status from some units */
data = gk20a_readl(g, gr_status_mask_r());
gk20a_writel(g, gr_status_mask_r(), data & gr->status_disable_mask);
gr_gk20a_load_zbc_table(g, gr); gr_gk20a_load_zbc_table(g, gr);
g->ops.ltc.init_cbc(g, gr); g->ops.ltc.init_cbc(g, gr);

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -279,8 +279,6 @@ struct gr_gk20a {
s32 max_used_color_index; s32 max_used_color_index;
s32 max_used_depth_index; s32 max_used_depth_index;
u32 status_disable_mask;
#define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */
struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
u32 channel_tlb_flush_index; u32 channel_tlb_flush_index;