nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 09:57:08 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: unit: increase coverage and docs for mm

Browse Source 
For common.mm subunits, this patch:
- adds extra test cases for some lesser used APIs
- updates SWUTS to add several functions to Targets fields.

JIRA NVGPU-3510

Change-Id: I350fbe0927472e1a07385a8cf87e0f0a8bbb6a8c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280067
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nicolas Benech
2020-01-16 13:45:41 -05:00
committed by Alex Waterman
parent a3d91c4f47
commit ea2563c033
17 changed files with 615 additions and 99 deletions
Download Patch File Download Diff File Expand all files Collapse all files

96
userspace/units/mm/gmmu/page_table/page_table.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -49,13 +49,14 @@
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
#define TEST_PA_ADDRESS 0xEFAD80000000
#define TEST_GPU_VA 0x102040600000
#define TEST_PA_ADDRESS_64K 0x1FAD80010000
#define TEST_PA_ADDRESS_4K 0x2FAD80001000
#define TEST_HOLE_SIZE 0x100000
#define TEST_COMP_TAG 0xEF
#define TEST_PA_ADDRESS 0xEFAD80000000
#define TEST_GPU_VA 0x102040600000
#define TEST_PA_ADDRESS_64K 0x1FAD80010000
#define TEST_PA_ADDRESS_4K 0x2FAD80001000
#define TEST_HOLE_SIZE 0x100000
#define TEST_COMP_TAG 0xEF
#define TEST_INVALID_ADDRESS 0xAAC0000000
#define TEST_PTE_SIZE 2U
/* Size of the buffer to map. It must be a multiple of 4KB */
#define TEST_SIZE (1 * SZ_1M)
@@ -366,13 +367,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
return UNIT_SUCCESS;
}
/*
* Test: test_nvgpu_gmmu_init
* This test must be run once and be the first oneas it initializes the MM
* subsystem.
*/
static int test_nvgpu_gmmu_init(struct unit_module *m,
struct gk20a *g, void *args)
int test_nvgpu_gmmu_init(struct unit_module *m, struct gk20a *g, void *args)
{
int debug_level = verbose_lvl(m);
@@ -396,12 +391,7 @@ static int test_nvgpu_gmmu_init(struct unit_module *m,
return UNIT_SUCCESS;
}
/*
* Test: test_nvgpu_gmmu_clean
* This test should be the last one to run as it de-initializes components.
*/
static int test_nvgpu_gmmu_clean(struct unit_module *m,
struct gk20a *g, void *args)
int test_nvgpu_gmmu_clean(struct unit_module *m, struct gk20a *g, void *args)
{
g->log_mask = 0;
nvgpu_vm_put(g->mm.pmu.vm);
@@ -455,7 +445,7 @@ int test_nvgpu_gmmu_map_unmap(struct unit_module *m, struct gk20a *g,
void *args)
{
struct nvgpu_mem mem = { };
u32 pte[2];
u32 pte[TEST_PTE_SIZE];
int result;
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
struct test_parameters *params = (struct test_parameters *) args;
@@ -624,12 +614,7 @@ int test_nvgpu_gmmu_map_unmap_map_fail(struct unit_module *m, struct gk20a *g,
return UNIT_SUCCESS;
}
/*
* Test: test_nvgpu_gmmu_init_page_table_fail
* Test special corner cases causing nvgpu_gmmu_init_page_table to fail
* Mostly to cover error handling and some branches.
*/
static int test_nvgpu_gmmu_init_page_table_fail(struct unit_module *m,
int test_nvgpu_gmmu_init_page_table_fail(struct unit_module *m,
struct gk20a *g, void *args)
{
int err;
@@ -648,16 +633,11 @@ static int test_nvgpu_gmmu_init_page_table_fail(struct unit_module *m,
return UNIT_SUCCESS;
}
/*
* Test: test_nvgpu_gmmu_set_pte
* This test targets the nvgpu_set_pte() function by mapping a buffer, and
* then trying to alter the validity bit of the corresponding PTE.
*/
static int test_nvgpu_gmmu_set_pte(struct unit_module *m,
struct gk20a *g, void *args)
int test_nvgpu_gmmu_set_pte(struct unit_module *m, struct gk20a *g, void *args)
{
struct nvgpu_mem mem = { };
u32 pte[2];
u32 pte[TEST_PTE_SIZE];
u32 pte_size;
int result;
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
struct test_parameters *params = (struct test_parameters *) args;
@@ -673,6 +653,12 @@ static int test_nvgpu_gmmu_set_pte(struct unit_module *m,
unit_return_fail(m, "Failed to map GMMU page");
}
pte_size = nvgpu_pte_words(g);
if (pte_size != TEST_PTE_SIZE) {
unit_return_fail(m, "PTE size unexpected: %d/%d\n", pte_size,
TEST_PTE_SIZE);
}
result = nvgpu_get_pte(g, g->mm.pmu.vm, mem.gpu_va, &pte[0]);
if (result != 0) {
unit_return_fail(m, "PTE lookup failed with code=%d\n", result);
@@ -869,11 +855,6 @@ int test_nvgpu_gmmu_map_unmap_adv(struct unit_module *m,
return UNIT_SUCCESS;
}
/*
* Test: test_nvgpu_gmmu_map_unmap_batched
* This tests uses the batch mode and maps 2 buffers. Then it checks that
* the flags in the batch structure were set correctly.
*/
int test_nvgpu_gmmu_map_unmap_batched(struct unit_module *m,
struct gk20a *g, void *args)
{
@@ -933,7 +914,7 @@ int test_nvgpu_gmmu_map_unmap_batched(struct unit_module *m,
static int check_pte_valid(struct unit_module *m, struct gk20a *g,
struct vm_gk20a *vm, struct nvgpu_mem *mem)
{
u32 pte[2];
u32 pte[TEST_PTE_SIZE];
int result;
result = nvgpu_get_pte(g, vm, mem->gpu_va, &pte[0]);
@@ -953,7 +934,7 @@ static int check_pte_valid(struct unit_module *m, struct gk20a *g,
static int check_pte_invalidated(struct unit_module *m, struct gk20a *g,
struct vm_gk20a *vm, struct nvgpu_mem *mem)
{
u32 pte[2];
u32 pte[TEST_PTE_SIZE];
int result;
result = nvgpu_get_pte(g, vm, mem->gpu_va, &pte[0]);
@@ -1179,6 +1160,36 @@ int test_nvgpu_page_table_c2_full(struct unit_module *m, struct gk20a *g,
return UNIT_SUCCESS;
}
int test_nvgpu_gmmu_perm_str(struct unit_module *m, struct gk20a *g, void *args)
{
int ret = UNIT_FAIL;
const char *str;
str = nvgpu_gmmu_perm_str(gk20a_mem_flag_none);
if (strcmp(str, "RW") != 0) {
unit_return_fail(m, "nvgpu_gmmu_perm_str failed (1)\n");
}
str = nvgpu_gmmu_perm_str(gk20a_mem_flag_write_only);
if (strcmp(str, "WO") != 0) {
unit_return_fail(m, "nvgpu_gmmu_perm_str failed (2)\n");
}
str = nvgpu_gmmu_perm_str(gk20a_mem_flag_read_only);
if (strcmp(str, "RO") != 0) {
unit_return_fail(m, "nvgpu_gmmu_perm_str failed (3)\n");
}
str = nvgpu_gmmu_perm_str(0xFF);
if (strcmp(str, "??") != 0) {
unit_return_fail(m, "nvgpu_gmmu_perm_str failed (4)\n");
}
ret = UNIT_SUCCESS;
return ret;
}
struct unit_module_test nvgpu_gmmu_tests[] = {
UNIT_TEST(gmmu_init, test_nvgpu_gmmu_init, (void *) 1, 0),
@@ -1285,6 +1296,7 @@ struct unit_module_test nvgpu_gmmu_tests[] = {
req_fixed_address, test_nvgpu_page_table_c2_full,
NULL, 0),
UNIT_TEST(gmmu_perm_str, test_nvgpu_gmmu_perm_str, NULL, 0),
UNIT_TEST(gmmu_clean, test_nvgpu_gmmu_clean, NULL, 0),
};

148
userspace/units/mm/gmmu/page_table/page_table.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -69,8 +69,8 @@ int test_nvgpu_gmmu_map_unmap_map_fail(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature
*
* Targets: nvgpu_gmmu_map_fixed, nvgpu_gmmu_map, nvgpu_get_pte,
* nvgpu_gmmu_unmap
* Targets: nvgpu_gmmu_map_fixed, gops_mm.gops_mm_gmmu.map, nvgpu_gmmu_map,
* nvgpu_get_pte, gops_mm.gops_mm_gmmu.unmap, nvgpu_gmmu_unmap
*
* Input: args as a struct test_parameters to hold scenario and test parameters.
*
@@ -103,7 +103,8 @@ int test_nvgpu_gmmu_map_unmap(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature
*
* Targets: nvgpu_gmmu_map_locked, nvgpu_gmmu_unmap
* Targets: gops_mm.gops_mm_gmmu.map, nvgpu_gmmu_map_locked,
* gops_mm.gops_mm_gmmu.unmap, nvgpu_gmmu_unmap, gk20a_from_vm
*
* Input: args as a struct test_parameters to hold scenario and test parameters.
*
@@ -128,7 +129,8 @@ int test_nvgpu_gmmu_map_unmap_adv(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature
*
* Targets: nvgpu_gmmu_map_locked, nvgpu_gmmu_unmap
* Targets: nvgpu_gmmu_map_locked, nvgpu_gmmu_unmap, gops_mm.gops_mm_gmmu.unmap,
* nvgpu_gmmu_unmap_locked
*
* Input: args as a struct test_parameters to hold scenario and test parameters.
*
@@ -157,8 +159,9 @@ int test_nvgpu_gmmu_map_unmap_batched(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature
*
* Targets: nvgpu_vm_init, nvgpu_gmmu_map, nvgpu_gmmu_map_locked,
* nvgpu_gmmu_unmap, nvgpu_vm_put
* Targets: nvgpu_vm_init, nvgpu_gmmu_map, gops_mm.gops_mm_gmmu.map,
* nvgpu_gmmu_map_locked, gops_mm.gops_mm_gmmu.unmap, nvgpu_gmmu_unmap,
* nvgpu_vm_put
*
* Input: None
*
@@ -189,8 +192,8 @@ int test_nvgpu_page_table_c1_full(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature
*
* Targets: nvgpu_vm_init, nvgpu_gmmu_map_fixed, nvgpu_gmmu_unmap,
* nvgpu_vm_put
* Targets: nvgpu_vm_init, gops_mm.gops_mm_gmmu.map, nvgpu_gmmu_map_fixed,
* gops_mm.gops_mm_gmmu.unmap, nvgpu_gmmu_unmap, nvgpu_vm_put
*
* Input: None
*
@@ -211,5 +214,132 @@ int test_nvgpu_page_table_c1_full(struct unit_module *m, struct gk20a *g,
int test_nvgpu_page_table_c2_full(struct unit_module *m, struct gk20a *g,
void *args);
/**
* Test specification for: test_nvgpu_gmmu_init_page_table_fail
*
* Description: Test special corner cases causing nvgpu_gmmu_init_page_table
* to fail, mostly to cover error handling and some branches.
*
* Test Type: Error injection
*
* Targets: nvgpu_gmmu_init_page_table
*
* Input: None
*
* Steps:
* - Enable KMEM fault injection.
* - Call nvgpu_gmmu_init_page_table.
* - Disable KMEM fault injection.
* - Ensure that nvgpu_gmmu_init_page_table failed as expected.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_nvgpu_gmmu_init_page_table_fail(struct unit_module *m,
struct gk20a *g, void *args);
/**
* Test specification for: test_nvgpu_gmmu_set_pte
*
* Description: This test targets the nvgpu_set_pte() function by mapping a
* buffer, and then trying to alter the validity bit of the corresponding PTE.
*
* Test Type: Feature, Error injection
*
* Targets: nvgpu_get_pte, nvgpu_set_pte, nvgpu_pte_words
*
* Input: None
*
* Steps:
* - Map a test buffer (dynamic) and get the assigned GPU VA.
* - Ensure the mapping succeeded.
* - Check that nvgpu_pte_words returns the expected value (2).
* - Use nvgpu_get_pte to retrieve the PTE from the assigned GPU VA, ensure
* it is valid.
* - Call nvgpu_set_pte with an invalid address and ensure it failed.
* - Using nvgpu_set_pte, rewrite the PTE with the validity bit flipped and
* ensure it reports success.
* - Retrieve the PTE again, ensure it succeeds and then check that the PTE
* is invalid.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
static int test_nvgpu_gmmu_set_pte(struct unit_module *m,
struct gk20a *g, void *args);
/**
* Test specification for: test_nvgpu_gmmu_init
*
* Description: This test must be run once and be the first one as it
* initializes the MM subsystem.
*
* Test Type: Other (setup), Feature
*
* Targets: nvgpu_gmmu_init_page_table, nvgpu_vm_init
*
* Input: None
*
* Steps:
* - Set debug log masks if needed.
* - For iGPU, enable the following flags: NVGPU_MM_UNIFIED_MEMORY,
* NVGPU_USE_COHERENT_SYSMEM, NVGPU_SUPPORT_NVLINK
* - Setup all the needed HALs.
* - Create a test PMU VM to be used by other tests which will cause the
* nvgpu_gmmu_init_page_table function to be called.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_nvgpu_gmmu_init(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_nvgpu_gmmu_clean
*
* Description: This test should be the last one to run as it de-initializes
* components.
*
* Test Type: Other (cleanup)
*
* Targets: None
*
* Input: None
*
* Steps:
* - Set log mask to 0.
* - Call nvgpu_vm_put to remove the test VM.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_nvgpu_gmmu_clean(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_nvgpu_gmmu_perm_str
*
* Description: Tests all supported combinations of permissions on the
* nvgpu_gmmu_perm_str function.
*
* Test Type: Feature
*
* Targets: nvgpu_gmmu_perm_str
*
* Input: None
*
* Steps:
* - Call nvgpu_gmmu_perm_str with flag gk20a_mem_flag_none and ensure it
* returns "RW"
* - Call nvgpu_gmmu_perm_str with flag gk20a_mem_flag_write_only and ensure it
* returns "WO"
* - Call nvgpu_gmmu_perm_str with flag gk20a_mem_flag_read_only and ensure it
* returns "RO"
* - Call nvgpu_gmmu_perm_str with an invalid flag and ensure it
* returns "??"
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_nvgpu_gmmu_perm_str(struct unit_module *m, struct gk20a *g,
void *args);
/** }@ */
#endif /* UNIT_PAGE_TABLE_H */