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gpu: nvgpu: vgpu: add getting gr constants

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move below attributes to constants:
TEGRA_VGPU_ATTRIB_GPC_COUNT
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT
TEGRA_VGPU_ATTRIB_NUM_FBPS
TEGRA_VGPU_ATTRIB_FBP_EN_MASK
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC

JIRA VFND-2103

Change-Id: Ic2ac14a0f8a1cf19a996bcef20bef0003d3b9a3b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1194630
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
This commit is contained in:
Richard Zhao
2016-07-26 17:48:58 -07:00
committed by mobile promotions
parent 843bbc726c
commit ead3148816
2 changed files with 29 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

53
drivers/gpu/nvgpu/vgpu/gr_vgpu.c
View File

@@ -631,29 +631,22 @@ static u32 vgpu_gr_get_gpc_tpc_count(struct gk20a *g, u32 gpc_index)
static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
{ {
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
u32 gpc_index; u32 gpc_index;
gk20a_dbg_fn(""); gk20a_dbg_fn("");
if (vgpu_get_attribute(vgpu_get_handle(g), gr->max_gpc_count = priv->constants.max_gpc_count;
TEGRA_VGPU_ATTRIB_GPC_COUNT, &gr->gpc_count)) gr->gpc_count = priv->constants.gpc_count;
return -ENOMEM; gr->max_tpc_per_gpc_count = priv->constants.max_tpc_per_gpc_count;
if (vgpu_get_attribute(vgpu_get_handle(g),
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT,
&gr->max_tpc_per_gpc_count))
return -ENOMEM;
if (vgpu_get_attribute(vgpu_get_handle(g),
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT,
&gr->max_tpc_count))
return -ENOMEM;
if (vgpu_get_attribute(vgpu_get_handle(g), if (vgpu_get_attribute(vgpu_get_handle(g),
TEGRA_VGPU_ATTRIB_TPC_COUNT, TEGRA_VGPU_ATTRIB_TPC_COUNT,
&gr->tpc_count)) &gr->tpc_count))
return -ENOMEM; return -ENOMEM;
gr->max_tpc_count = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
gr->gpc_tpc_count = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL); gr->gpc_tpc_count = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
if (!gr->gpc_tpc_count) if (!gr->gpc_tpc_count)
goto cleanup; goto cleanup;
@@ -682,7 +675,7 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
g->ops.gr.init_fs_state(g); g->ops.gr.init_fs_state(g);
return 0; return 0;
cleanup: cleanup:
gk20a_err(dev_from_gk20a(g), "%s: out of memory\n", __func__); gk20a_err(dev_from_gk20a(g), "%s: out of memory", __func__);
kfree(gr->gpc_tpc_count); kfree(gr->gpc_tpc_count);
gr->gpc_tpc_count = NULL; gr->gpc_tpc_count = NULL;
@@ -759,54 +752,38 @@ static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)
{ {
u32 max_fbps_count = 0; struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gk20a_dbg_fn(""); gk20a_dbg_fn("");
if (vgpu_get_attribute(vgpu_get_handle(g), return priv->constants.num_fbps;
TEGRA_VGPU_ATTRIB_NUM_FBPS, &max_fbps_count))
gk20a_err(dev_from_gk20a(g), "failed to retrieve num fbps");
return max_fbps_count;
} }
static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g)
{ {
u32 fbp_en_mask = 0; struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gk20a_dbg_fn(""); gk20a_dbg_fn("");
if (vgpu_get_attribute(vgpu_get_handle(g), return priv->constants.fbp_en_mask;
TEGRA_VGPU_ATTRIB_FBP_EN_MASK, &fbp_en_mask))
gk20a_err(dev_from_gk20a(g), "failed to retrieve fbp en mask");
return fbp_en_mask;
} }
static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g)
{ {
u32 val = 0; struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gk20a_dbg_fn(""); gk20a_dbg_fn("");
if (vgpu_get_attribute(vgpu_get_handle(g), return priv->constants.ltc_per_fbp;
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, &val))
gk20a_err(dev_from_gk20a(g), "failed to retrieve max ltc per fbp");
return val;
} }
static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
{ {
u32 val = 0; struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
gk20a_dbg_fn(""); gk20a_dbg_fn("");
if (vgpu_get_attribute(vgpu_get_handle(g), return priv->constants.max_lts_per_ltc;
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, &val))
gk20a_err(dev_from_gk20a(g), "failed to retrieve lts per ltc");
return val;
} }
static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g)

21
include/linux/tegra_vgpu.h
View File

@@ -115,22 +115,22 @@ enum {
TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */ TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */ TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */ TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */ TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */ TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, /* deprecated */
TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14,
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */ TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */ TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */ TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */ TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
}; };
@@ -420,6 +420,13 @@ struct tegra_vgpu_constants_params {
u32 sm_arch_sm_version; u32 sm_arch_sm_version;
u32 sm_arch_spa_version; u32 sm_arch_spa_version;
u32 sm_arch_warp_count; u32 sm_arch_warp_count;
u32 max_gpc_count;
u32 gpc_count;
u32 max_tpc_per_gpc_count;
u32 num_fbps;
u32 fbp_en_mask;
u32 ltc_per_fbp;
u32 max_lts_per_ltc;
}; };
struct tegra_vgpu_cmd_msg { struct tegra_vgpu_cmd_msg {