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gpu: nvgpu: add ioctl to configure implicit ERRBAR

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Add ioctl support to configure implicit ERRBAR by setting/unsetting
NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED register.

Add gpu characteritics flag: NVGPU_SCHED_EXIT_WAIT_FOR_ERRBAR_SUPPORTED
to allow userspace driver to determine if implicit ERRBAR ioctl is
supported.

Bug: 200782861

Change-Id: I530a4cf73bc5c844e8d73094d3e23949568fe335
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2718672
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
atanand
2022-05-26 09:34:15 +00:00
committed by mobile promotions
parent faf18009cb
commit eae4593343
15 changed files with 181 additions and 2 deletions
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4
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -548,6 +548,10 @@ struct nvgpu_channel {
* MMU Debugger Mode is enabled for this channel if refcnt > 0
*/
u32 mmu_debug_mode_refcnt;
/**
* ERRBAR is enabled for this channel if refcnt > 0
*/
nvgpu_atomic_t sched_exit_wait_for_errbar_refcnt;
#endif
};

2
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -228,6 +228,8 @@ struct gk20a;
"Emulate mode support"), \
DEFINE_FLAG(NVGPU_SUPPORT_PES_FS, \
"PES Floorsweeping"), \
DEFINE_FLAG(NVGPU_SCHED_EXIT_WAIT_FOR_ERRBAR_SUPPORTED, \
"Implicit ERRBAR support"), \
DEFINE_FLAG(NVGPU_MAX_ENABLED_BITS, "Marks max number of flags"),
/**

2
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -1367,6 +1367,8 @@ struct gops_gr {
u32 num_ppcs, u32 ppc_mask,
u32 *priv_offset);
void (*set_debug_mode)(struct gk20a *g, bool enable);
int (*set_sched_wait_for_errbar)(struct gk20a *g,
struct nvgpu_channel *ch, bool enable);
int (*set_mmu_debug_mode)(struct gk20a *g,
struct nvgpu_channel *ch, bool enable);
bool (*esr_bpt_pending_events)(u32 global_esr,

9
drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1258,4 +1258,11 @@
#define gr_gpcs_tpcs_sm_l1tag_ctrl_surface_cut_collector_enable_f()\
(0x20000000U)
#define gr_gpc0_tpc0_sm_l1tag_ctrl_r() (0x005043f0U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_r() (0x00419b48U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_m()\
(U32(0x1U) << 20U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_enabled_f()\
(0x100000U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_disabled_f()\
(0x0U)
#endif

7
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
View File

@@ -1247,4 +1247,11 @@
#define gr_gpcs_tpcs_sm_l1tag_ctrl_surface_cut_collector_enable_f()\
(0x20000000U)
#define gr_gpc0_tpc0_sm_l1tag_ctrl_r() (0x005043f0U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_r() (0x00419b48U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_m()\
(U32(0x1U) << 20U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_enabled_f()\
(0x100000U)
#define gr_gpcs_pri_tpcs_sm_sch_macro_sched_exit_wait_for_errbar_disabled_f()\
(0x0U)
#endif

4
drivers/gpu/nvgpu/include/nvgpu/tsg.h
View File

@@ -210,6 +210,9 @@ struct nvgpu_tsg {
/** MMU debug mode enabled if mmu_debug_mode_refcnt > 0 */
u32 mmu_debug_mode_refcnt;
/** ERRBAR enabled if sched_exit_wait_for_errbar_refcnt > 0 */
nvgpu_atomic_t sched_exit_wait_for_errbar_refcnt;
/**
* Pointer to store SM errors read from h/w registers.
* Check #nvgpu_tsg_sm_error_state.
@@ -754,5 +757,6 @@ void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg,
bool eng, bool pbdma);
#ifdef CONFIG_NVGPU_DEBUGGER
int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_channel *ch, bool enable);
int nvgpu_tsg_set_sched_exit_wait_for_errbar(struct nvgpu_channel *ch, bool enable);
#endif
#endif /* NVGPU_TSG_H */