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gpu: nvgpu: add ioctl to configure implicit ERRBAR

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Add ioctl support to configure implicit ERRBAR by setting/unsetting
NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED register.

Add gpu characteritics flag: NVGPU_SCHED_EXIT_WAIT_FOR_ERRBAR_SUPPORTED
to allow userspace driver to determine if implicit ERRBAR ioctl is
supported.

Bug: 200782861

Change-Id: I530a4cf73bc5c844e8d73094d3e23949568fe335
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2718672
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
atanand
2022-05-26 09:34:15 +00:00
committed by mobile promotions
parent faf18009cb
commit eae4593343
15 changed files with 181 additions and 2 deletions
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50
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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@@ -1235,6 +1235,51 @@ clean_up:
return err;
}
static int nvgpu_dbg_gpu_set_sched_wait_for_errbar(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_sched_exit_wait_for_errbar_args *args)
{
int err;
struct gk20a *g = dbg_s->g;
struct nvgpu_channel *ch;
bool enable = (args->enable == NVGPU_DBG_GPU_SCHED_EXIT_WAIT_FOR_ERRBAR_ENABLED);
u32 gr_instance_id =
nvgpu_grmgr_get_gr_instance_id(g, dbg_s->gpu_instance_id);
nvgpu_log_fn(g, "enable=%u", args->enable);
if (g->ops.gr.set_sched_wait_for_errbar == NULL) {
return -ENOSYS;
}
err = gk20a_busy(g);
if (err) {
nvgpu_err(g, "failed to poweron, err=%d", err);
return err;
}
/* Take the global lock, since we'll be doing global regops */
nvgpu_mutex_acquire(&g->dbg_sessions_lock);
ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
if (ch == NULL) {
nvgpu_err(g, "no bound channel for mmu debug mode");
err = -EINVAL;
goto clean_up;
}
err = nvgpu_gr_exec_with_err_for_instance(g, gr_instance_id,
nvgpu_tsg_set_sched_exit_wait_for_errbar(ch, enable));
if (err) {
nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
}
clean_up:
nvgpu_mutex_release(&g->dbg_sessions_lock);
gk20a_idle(g);
return err;
}
static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args)
@@ -2931,6 +2976,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
(struct nvgpu_dbg_gpu_va_access_args *)buf);
break;
case NVGPU_DBG_GPU_IOCTL_SET_SCHED_EXIT_WAIT_FOR_ERRBAR:
err = nvgpu_dbg_gpu_set_sched_wait_for_errbar(dbg_s,
(struct nvgpu_sched_exit_wait_for_errbar_args *)buf);
break;
default:
nvgpu_err(g,
"unrecognized dbg gpu ioctl cmd: 0x%x",