From ebc0b3b38166dee22c413c27a96d03af9bf5558a Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Thu, 6 Jun 2019 09:46:03 +0530 Subject: [PATCH] gpu: nvgpu: Remove hardcoding related to Psate objs In P4 #25076323, we have done many hard codings in PMU which are related to Pstate board objs. As we are sending Pstate objs now we can remove those hardcoding in NVGPU. NVGPU-3597 Change-Id: I8b35e6b34c71721bb84fde9ffc280cf748232dbf Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/2131350 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/clk/clk.c | 7 +++++-- drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c | 6 ++++-- .../gpu/nvgpu/common/pmu/perf/change_seq.c | 7 +++++-- .../gpu/nvgpu/common/pmu/perf/perf_pstate.c | 19 +++++++++++++++++++ .../include/nvgpu/pmu/pmuif/perfpstate.h | 1 + 5 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index d5fda8333..ec01cd779 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -33,6 +33,7 @@ #include #include #include +#include void nvgpu_clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, void *param, u32 status) @@ -291,7 +292,8 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, g->pmu->clk_pmu->set_p0_clks(g, &gpcclk_domain, &gpcclk_clkmhz, vf_point, &change_input); - change_input.pstate_index = 0U; + change_input.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; change_input.vf_points_cache_counter = 0xFFFFFFFFU; @@ -334,7 +336,8 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, (void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_perf_change_seq_queue_change)); rpc.change = change_input; - rpc.change.pstate_index = 0; + rpc.change.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); PMU_RPC_EXECUTE_CPB(status, pmu, PERF, CHANGE_SEQ_QUEUE_CHANGE, &rpc, 0); if (status != 0) { diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c index ec8868794..846b05c59 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c @@ -1503,7 +1503,8 @@ static int clk_set_boot_fll_clks_per_clk_domain(struct gk20a *g) } } - change_input.pstate_index = 0U; + change_input.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); change_input.flags = (u32)CTRL_PERF_CHANGE_SEQ_CHANGE_FORCE; change_input.vf_points_cache_counter = 0xFFFFFFFFU; @@ -1533,7 +1534,8 @@ static int clk_set_boot_fll_clks_per_clk_domain(struct gk20a *g) (void) memset(&rpc, 0, sizeof( struct nv_pmu_rpc_perf_change_seq_queue_change)); rpc.change = change_input; - rpc.change.pstate_index = 0; + rpc.change.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); PMU_RPC_EXECUTE_CPB(status, pmu, PERF, CHANGE_SEQ_QUEUE_CHANGE, &rpc, 0); if (status != 0) { diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c index 93bd7f8e5..20382105a 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "pmu_perf.h" #include "change_seq.h" @@ -158,7 +159,8 @@ static void build_change_seq_boot (struct gk20a *g) script_last->buf.change.data.clk_list.num_domains); /* Assume everything is P0 - Need to find the index for P0 */ - script_last->buf.change.data.pstate_index = 0; + script_last->buf.change.data.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0); nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g, pmu, pmu->super_surface), @@ -236,7 +238,8 @@ int nvgpu_perf_change_seq_pmu_setup(struct gk20a *g) (u32) sizeof(struct perf_change_seq_pmu_script)); /* Assume everything is P0 - Need to find the index for P0 */ - perf_change_seq_pmu->script_last.buf.change.data.pstate_index = 0; + perf_change_seq_pmu->script_last.buf.change.data.pstate_index = + nvgpu_get_pstate_entry_idx(g, CTRL_PERF_PSTATE_P0);; nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g, pmu, pmu->super_surface), diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c index f4e6f69e6..26a26eda3 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c @@ -37,6 +37,25 @@ #include "perf_pstate.h" +int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num) +{ + struct pstates *pstates = &(g->perf_pmu->pstatesobjs); + struct pstate *pstate; + u8 i; + + nvgpu_log_info(g, "pstates = %p", pstates); + + BOARDOBJGRP_FOR_EACH(&pstates->super.super, + struct pstate *, pstate, i) { + nvgpu_log_info(g, "pstate=%p num=%u (looking for num=%u)", + pstate, pstate->num, num); + if (pstate->num == num) { + return i; + } + } + return 0; +} + static int pstate_init_pmudata_super(struct gk20a *g, struct boardobj *board_obj_ptr, struct nv_pmu_boardobj *ppmudata) diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfpstate.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfpstate.h index 681afff7b..a0cef029a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfpstate.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfpstate.h @@ -124,5 +124,6 @@ struct nv_pmu_perf_pstate_status { clkDomains[PMU_PERF_CLK_DOMAINS_IDX_MAX]; }; +int nvgpu_get_pstate_entry_idx(struct gk20a *g, u32 num); #endif /* NVGPU_PMUIF_PERFPSTATE_H_ */