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gpu: nvgpu: move non-safe functions from fusa hal to non-fusa hal

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Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.

JIRA NVGPU-3853

Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-09-24 11:34:38 +05:30
committed by Alex Waterman
parent e5259f5819
commit ec293030c1
26 changed files with 917 additions and 806 deletions
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34
drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
View File

@@ -91,3 +91,37 @@ u64 gm20b_fb_compression_align_mask(struct gk20a *g)
return SZ_64K - 1UL;
}
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
{
u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
return fb_mmu_debug_ctrl_debug_v(debug_ctrl) ==
fb_mmu_debug_ctrl_debug_enabled_v();
}
void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
{
u32 reg_val, fb_debug_ctrl;
if (enable) {
fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
g->mmu_debug_ctrl = true;
} else {
fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
g->mmu_debug_ctrl = false;
}
reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
reg_val = set_field(reg_val,
fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
}
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
{
gm20b_fb_set_mmu_debug_mode(g, enable);
g->ops.gr.set_debug_mode(g, enable);
}
#endif

33
drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c
View File

@@ -42,39 +42,6 @@
#define VPR_INFO_FETCH_WAIT (5)
#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
{
u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
return fb_mmu_debug_ctrl_debug_v(debug_ctrl) ==
fb_mmu_debug_ctrl_debug_enabled_v();
}
void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
{
u32 reg_val, fb_debug_ctrl;
if (enable) {
fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
g->mmu_debug_ctrl = true;
} else {
fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
g->mmu_debug_ctrl = false;
}
reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
reg_val = set_field(reg_val,
fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
}
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
{
gm20b_fb_set_mmu_debug_mode(g, enable);
g->ops.gr.set_debug_mode(g, enable);
}
#endif
void gm20b_fb_init_hw(struct gk20a *g)
{
u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;

102
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b.c Normal file
View File

@@ -0,0 +1,102 @@
/*
* GV11B ECC INTR
*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_err.h>
#include "fb_intr_ecc_gv11b.h"
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
void gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
unsigned int reg_addr = err->get_reg_addr();
nvgpu_info(g, "Injecting HUBMMU fault %s", err->name);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
}
static inline u32 l2tlb_ecc_control_r(void)
{
return fb_mmu_l2tlb_ecc_control_r();
}
static inline u32 l2tlb_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(v);
}
static inline u32 hubtlb_ecc_control_r(void)
{
return fb_mmu_hubtlb_ecc_control_r();
}
static inline u32 hubtlb_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_hubtlb_ecc_control_inject_uncorrected_err_f(v);
}
static inline u32 fillunit_ecc_control_r(void)
{
return fb_mmu_fillunit_ecc_control_r();
}
static inline u32 fillunit_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_fillunit_ecc_control_inject_uncorrected_err_f(v);
}
static struct nvgpu_hw_err_inject_info hubmmu_ecc_err_desc[] = {
NVGPU_ECC_ERR("hubmmu_l2tlb_sa_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
l2tlb_ecc_control_r,
l2tlb_ecc_control_inject_uncorrected_err_f),
NVGPU_ECC_ERR("hubmmu_tlb_sa_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
hubtlb_ecc_control_r,
hubtlb_ecc_control_inject_uncorrected_err_f),
NVGPU_ECC_ERR("hubmmu_pte_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
fillunit_ecc_control_r,
fillunit_ecc_control_inject_uncorrected_err_f),
};
static struct nvgpu_hw_err_inject_info_desc hubmmu_err_desc;
struct nvgpu_hw_err_inject_info_desc *
gv11b_fb_intr_get_hubmmu_err_desc(struct gk20a *g)
{
hubmmu_err_desc.info_ptr = hubmmu_ecc_err_desc;
hubmmu_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
sizeof(hubmmu_ecc_err_desc) /
sizeof(struct nvgpu_hw_err_inject_info));
return &hubmmu_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */

70
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c
View File

@@ -31,76 +31,6 @@
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
void gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
unsigned int reg_addr = err->get_reg_addr();
nvgpu_info(g, "Injecting HUBMMU fault %s", err->name);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
}
static inline u32 l2tlb_ecc_control_r(void)
{
return fb_mmu_l2tlb_ecc_control_r();
}
static inline u32 l2tlb_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(v);
}
static inline u32 hubtlb_ecc_control_r(void)
{
return fb_mmu_hubtlb_ecc_control_r();
}
static inline u32 hubtlb_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_hubtlb_ecc_control_inject_uncorrected_err_f(v);
}
static inline u32 fillunit_ecc_control_r(void)
{
return fb_mmu_fillunit_ecc_control_r();
}
static inline u32 fillunit_ecc_control_inject_uncorrected_err_f(u32 v)
{
return fb_mmu_fillunit_ecc_control_inject_uncorrected_err_f(v);
}
static struct nvgpu_hw_err_inject_info hubmmu_ecc_err_desc[] = {
NVGPU_ECC_ERR("hubmmu_l2tlb_sa_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
l2tlb_ecc_control_r,
l2tlb_ecc_control_inject_uncorrected_err_f),
NVGPU_ECC_ERR("hubmmu_tlb_sa_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
hubtlb_ecc_control_r,
hubtlb_ecc_control_inject_uncorrected_err_f),
NVGPU_ECC_ERR("hubmmu_pte_data_ecc_uncorrected",
gv11b_fb_intr_inject_hubmmu_ecc_error,
fillunit_ecc_control_r,
fillunit_ecc_control_inject_uncorrected_err_f),
};
static struct nvgpu_hw_err_inject_info_desc hubmmu_err_desc;
struct nvgpu_hw_err_inject_info_desc *
gv11b_fb_intr_get_hubmmu_err_desc(struct gk20a *g)
{
hubmmu_err_desc.info_ptr = hubmmu_ecc_err_desc;
hubmmu_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
sizeof(hubmmu_ecc_err_desc) /
sizeof(struct nvgpu_hw_err_inject_info));
return &hubmmu_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */
static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
{
u32 ecc_addr, corrected_cnt, uncorrected_cnt;