Open source GPL/LGPL release

drivers/gpu/nvgpu/common/acr/acr_blob_alloc.c

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/gk20a.h>
+
+#include "acr_wpr.h"
+#include "acr_priv.h"
+#include "acr_blob_alloc.h"
+
+int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size,
+	struct nvgpu_mem *mem)
+{
+	return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_PHYSICALLY_ADDRESSED,
+		size, mem);
+}
+#ifdef CONFIG_NVGPU_DGPU
+int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size,
+	struct nvgpu_mem *mem)
+{
+	struct wpr_carveout_info wpr_inf;
+	int err;
+
+	if (mem->size != 0ULL) {
+		return 0;
+	}
+
+	g->acr->get_wpr_info(g, &wpr_inf);
+
+	/*
+	 * Even though this mem_desc wouldn't be used, the wpr region needs to
+	 * be reserved in the allocator.
+	 */
+	err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size,
+		&g->acr->wpr_dummy, wpr_inf.wpr_base);
+	if (err != 0) {
+		return err;
+	}
+
+	return nvgpu_dma_alloc_vid_at(g, wpr_inf.size, mem,
+		wpr_inf.nonwpr_base);
+}
+#endif