From ecab3ddbce2dc1200d5a2fdde419bd1f6a4fd8e7 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 19 Nov 2019 18:06:20 -0500 Subject: [PATCH] gpu: nvgpu: unit: add tests for gv11b pbdma HAL Add tests for the following HALs: - gv11b_pbdma_setup_hw - gv11b_pbdma_intr_enable - gv11b_pbdma_handle_intr_0 - gv11b_pbdma_handle_intr_1 - gv11b_pbdma_channel_fatal_0_intr_descs - gv11b_pbdma_get_fc_pb_header - gv11b_pbdma_get_fc_target - gv11b_pbdma_set_channel_info_veid - gv11b_pbdma_config_userd_writeback_enable Jira NVGPU-3694 Change-Id: Ieea746e07cae4a3c1b5289674d93654edf7de941 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2253633 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- Makefile.umbrella.tmk | 1 + drivers/gpu/nvgpu/libnvgpu-drv_safe.export | 10 + userspace/Makefile.sources | 3 +- userspace/SWUTS.h | 1 + userspace/SWUTS.sources | 1 + userspace/units/fifo/pbdma/gv11b/Makefile | 32 ++ .../fifo/pbdma/gv11b/Makefile.interface.tmk | 35 ++ userspace/units/fifo/pbdma/gv11b/Makefile.tmk | 40 ++ .../fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c | 377 ++++++++++++++++++ .../fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h | 225 +++++++++++ 10 files changed, 724 insertions(+), 1 deletion(-) create mode 100644 userspace/units/fifo/pbdma/gv11b/Makefile create mode 100644 userspace/units/fifo/pbdma/gv11b/Makefile.interface.tmk create mode 100644 userspace/units/fifo/pbdma/gv11b/Makefile.tmk create mode 100644 userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c create mode 100644 userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 73065a342..a15a5375c 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -80,6 +80,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gp10b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv100 NV_REPOSITORY_COMPONENTS += userspace/units/fifo/engine/gv11b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma +NV_REPOSITORY_COMPONENTS += userspace/units/fifo/pbdma/gv11b NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist/gk20a NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist/gv11b diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 13baad4de..b3b44fffe 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -85,6 +85,15 @@ gv11b_mm_l2_flush gv11b_mm_mmu_fault_disable_hw gv11b_mm_mmu_fault_info_mem_destroy gv11b_mc_is_mmu_fault_pending +gv11b_pbdma_channel_fatal_0_intr_descs +gv11b_pbdma_config_userd_writeback_enable +gv11b_pbdma_get_fc_pb_header +gv11b_pbdma_get_fc_target +gv11b_pbdma_handle_intr_0 +gv11b_pbdma_handle_intr_1 +gv11b_pbdma_intr_enable +gv11b_pbdma_set_channel_info_veid +gv11b_pbdma_setup_hw gv11b_runlist_entry_size gv11b_runlist_get_tsg_entry gv11b_runlist_get_ch_entry @@ -412,6 +421,7 @@ nvgpu_pd_free nvgpu_pd_gpu_addr nvgpu_pd_offset_from_index nvgpu_pd_write +nvgpu_platform_is_silicon nvgpu_pmu_early_init nvgpu_pmu_remove_support nvgpu_pmu_reset diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index c8934ad58..ef510e5d0 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -82,12 +82,13 @@ UNITS := \ $(UNIT_SRC)/fifo/channel/gk20a \ $(UNIT_SRC)/fifo/channel/gm20b \ $(UNIT_SRC)/fifo/channel/gv11b \ - $(UNIT_SRC)/fifo/pbdma \ $(UNIT_SRC)/fifo/engine \ $(UNIT_SRC)/fifo/engine/gm20b \ $(UNIT_SRC)/fifo/engine/gp10b \ $(UNIT_SRC)/fifo/engine/gv100 \ $(UNIT_SRC)/fifo/engine/gv11b \ + $(UNIT_SRC)/fifo/pbdma \ + $(UNIT_SRC)/fifo/pbdma/gv11b \ $(UNIT_SRC)/fifo/runlist \ $(UNIT_SRC)/fifo/runlist/gk20a \ $(UNIT_SRC)/fifo/runlist/gv11b \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index 28671dd8d..b10b12f2f 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -47,6 +47,7 @@ * - @ref SWUTS-fifo-engine-gv100 * - @ref SWUTS-fifo-engine-gv11b * - @ref SWUTS-fifo-pbdma + * - @ref SWUTS-fifo-pbdma-gv11b * - @ref SWUTS-fifo-runlist * - @ref SWUTS-fifo-runlist-gk20a * - @ref SWUTS-fifo-runlist-gv11b diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index 7bc6b1d72..7cf21507b 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -17,6 +17,7 @@ INPUT += ../../../userspace/units/fifo/engine/gp10b/nvgpu-engine-gp10b.h INPUT += ../../../userspace/units/fifo/engine/gv100/nvgpu-engine-gv100.h INPUT += ../../../userspace/units/fifo/engine/gv11b/nvgpu-engine-gv11b.h INPUT += ../../../userspace/units/fifo/pbdma/nvgpu-pbdma.h +INPUT += ../../../userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h INPUT += ../../../userspace/units/fifo/runlist/nvgpu-runlist.h INPUT += ../../../userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.h INPUT += ../../../userspace/units/fifo/runlist/gv11b/nvgpu-runlist-gv11b.h diff --git a/userspace/units/fifo/pbdma/gv11b/Makefile b/userspace/units/fifo/pbdma/gv11b/Makefile new file mode 100644 index 000000000..bf57d598d --- /dev/null +++ b/userspace/units/fifo/pbdma/gv11b/Makefile @@ -0,0 +1,32 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-pbdma-gv11b.o +MODULE = nvgpu-pbdma-gv11b + +LIB_PATHS += -lnvgpu-fifo +include ../../../Makefile.units + +lib$(MODULE).so: fifo + +fifo: + $(MAKE) -C ../.. diff --git a/userspace/units/fifo/pbdma/gv11b/Makefile.interface.tmk b/userspace/units/fifo/pbdma/gv11b/Makefile.interface.tmk new file mode 100644 index 000000000..189daf97b --- /dev/null +++ b/userspace/units/fifo/pbdma/gv11b/Makefile.interface.tmk @@ -0,0 +1,35 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-pbdma-gv11b + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/pbdma/gv11b/Makefile.tmk b/userspace/units/fifo/pbdma/gv11b/Makefile.tmk new file mode 100644 index 000000000..5df005ff9 --- /dev/null +++ b/userspace/units/fifo/pbdma/gv11b/Makefile.tmk @@ -0,0 +1,40 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME = nvgpu-pbdma-gv11b +NVGPU_UNIT_SRCS = nvgpu-pbdma-gv11b.c + +NVGPU_UNIT_INTERFACE_DIRS := \ + $(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \ + $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu + +include $(NV_SOURCE)/kernel/nvgpu/userspace/units/Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c new file mode 100644 index 000000000..625939148 --- /dev/null +++ b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "hal/init/hal_gv11b.h" +#include "hal/fifo/pbdma_gv11b.h" + +#include + +#include + +#include "../../nvgpu-fifo.h" +#include "../../nvgpu-fifo-gv11b.h" +#include "nvgpu-pbdma-gv11b.h" + +#ifdef PBDMA_GV11B_UNIT_DEBUG +#undef unit_verbose +#define unit_verbose unit_info +#else +#define unit_verbose(unit, msg, ...) \ + do { \ + if (0) { \ + unit_info(unit, msg, ##__VA_ARGS__); \ + } \ + } while (0) +#endif + +#define assert(cond) unit_assert(cond, goto done) + +#define branches_str test_fifo_flags_str +#define pruned test_fifo_subtest_pruned + +struct unit_ctx { + struct unit_module *m; +}; + +int test_gv11b_pbdma_setup_hw(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 num_pbdma; + u32 pbdma_id; + u32 timeout; + + num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + assert(num_pbdma > 0); + + gv11b_pbdma_setup_hw(g); + if (nvgpu_platform_is_silicon(g)) { + for (pbdma_id = 0; pbdma_id < num_pbdma; pbdma_id++) + { + timeout = nvgpu_readl(g, pbdma_timeout_r(pbdma_id)); + assert(get_field(timeout, pbdma_timeout_period_m()) == + pbdma_timeout_period_max_f()); + } + } + + ret = UNIT_SUCCESS; +done: + + return ret; +} + +int test_gv11b_pbdma_intr_enable(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 num_pbdma; + u32 pbdma_id; + bool enable; + u32 i; + + num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + assert(num_pbdma > 0); + + for (i = 0 ; i < 2; i++) { + enable = (i > 0); + + for (pbdma_id = 0; pbdma_id < num_pbdma; pbdma_id++) { + u32 pattern = (0xbeef << 16) + pbdma_id; + nvgpu_writel(g, pbdma_intr_stall_r(pbdma_id), pattern); + nvgpu_writel(g, pbdma_intr_en_0_r(pbdma_id), 0); + nvgpu_writel(g, pbdma_intr_stall_1_r(pbdma_id), + pattern | pbdma_intr_stall_1_hce_illegal_op_enabled_f()); + nvgpu_writel(g, pbdma_intr_en_1_r(pbdma_id), 0); + } + + gv11b_pbdma_intr_enable(g, enable); + + for (pbdma_id = 0; pbdma_id < num_pbdma; pbdma_id++) { + u32 pattern = (0xbeef << 16) + pbdma_id; + u32 intr_0 = nvgpu_readl(g, pbdma_intr_stall_r(pbdma_id)); + u32 intr_1 = nvgpu_readl(g, pbdma_intr_stall_1_r(pbdma_id)); + u32 intr_en_0 = nvgpu_readl(g, pbdma_intr_en_0_r(pbdma_id)); + u32 intr_en_1 = nvgpu_readl(g, pbdma_intr_en_1_r(pbdma_id)); + + if (enable) { + assert(intr_en_0 == pattern); + assert(intr_en_1 == (pattern & + ~pbdma_intr_stall_1_hce_illegal_op_enabled_f())); + } else { + assert(intr_en_0 == 0); + assert(intr_en_1 == 0); + } + assert(intr_0 != 0); + assert(intr_1 != 0); + } + } + + ret = UNIT_SUCCESS; +done: + + return ret; +} + +#define PBDMA_NUM_INTRS_0 3 +#define INVALID_ERR_NOTIFIER U32_MAX + +static u32 pbdma_method_r(u32 pbdma_id, u32 method_index) +{ + u32 stride = pbdma_method1_r(pbdma_id) - pbdma_method0_r(pbdma_id); + return pbdma_method0_r(pbdma_id) + stride * method_index; +} + +int test_gv11b_pbdma_handle_intr_0(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_fifo *f = &g->fifo; + struct gpu_ops gops = g->ops; + u32 branches = 0; + u32 pbdma_intrs[PBDMA_NUM_INTRS_0] = { + pbdma_intr_0_memreq_pending_f(), + pbdma_intr_0_clear_faulted_error_pending_f(), + pbdma_intr_0_eng_reset_pending_f(), + }; + const char *labels[] = { + "memreq", + "clear_faulted", + "eng_reset", + }; + u32 pbdma_id = 0; + u32 pbdma_intr_0; + u32 err_notifier; + bool recover; + int i; + + assert((f->intr.pbdma.device_fatal_0 & pbdma_intr_0_memreq_pending_f()) != 0); + + for (branches = 0; branches < BIT(PBDMA_NUM_INTRS_0); branches++) { + + unit_verbose(m, "%s branches=%s\n", __func__, + branches_str(branches, labels)); + + pbdma_intr_0 = 0; + for (i = 0; i < PBDMA_NUM_INTRS_0; i++) { + if (branches & BIT(i)) { + pbdma_intr_0 |= pbdma_intrs[i]; + } + } + err_notifier = INVALID_ERR_NOTIFIER; + + nvgpu_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); + nvgpu_writel(g, pbdma_method_r(pbdma_id, 0), 0); + + recover = gv11b_pbdma_handle_intr_0(g, pbdma_id, pbdma_intr_0, &err_notifier); + + if (pbdma_intr_0 == 0) { + assert(!recover); + } + + if (pbdma_intr_0 & pbdma_intr_0_memreq_pending_f()) { + assert(recover); + } + + if (pbdma_intr_0 & pbdma_intr_0_clear_faulted_error_pending_f()) { + assert(recover); + assert(nvgpu_readl(g, pbdma_method_r(pbdma_id, 0)) != 0); + } else { + assert(nvgpu_readl(g, pbdma_method_r(pbdma_id, 0)) == 0); + } + + if (pbdma_intr_0 & pbdma_intr_0_eng_reset_pending_f()) { + assert(recover); + } + + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s branches=%s\n", __func__, + branches_str(branches, labels)); + } + g->ops = gops; + return ret; +} + +#define F_PBDMA_INTR_1_CTXNOTVALID_IN BIT(0) +#define F_PBDMA_INTR_1_CTXNOTVALID_READ BIT(1) +#define F_PBDMA_INTR_1_LAST BIT(2) + +int test_gv11b_pbdma_handle_intr_1(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 branches; + const char *labels[] = { + "ctxnotvalid_in", + "ctxnotvalid_readl", + }; + u32 pbdma_id = 0; + u32 pbdma_intr_1; + u32 err_notifier; + bool recover; + + for (branches = 0; branches < F_PBDMA_INTR_1_LAST; branches++) { + + unit_verbose(m, "%s branches=%s\n", __func__, + branches_str(branches, labels)); + + pbdma_intr_1 = 0; + + if (branches & F_PBDMA_INTR_1_CTXNOTVALID_IN) { + pbdma_intr_1 |= pbdma_intr_1_ctxnotvalid_pending_f(); + } + + if (branches & F_PBDMA_INTR_1_CTXNOTVALID_READ) { + nvgpu_writel(g, pbdma_intr_1_r(pbdma_id), + pbdma_intr_1_ctxnotvalid_pending_f()); + } else { + nvgpu_writel(g, pbdma_intr_1_r(pbdma_id), 0); + } + + err_notifier = INVALID_ERR_NOTIFIER; + + recover = gv11b_pbdma_handle_intr_1(g, pbdma_id, pbdma_intr_1, &err_notifier); + + if (pbdma_intr_1 == 0) { + assert(!recover); + } + + if ((branches & F_PBDMA_INTR_1_CTXNOTVALID_IN) && + (branches & F_PBDMA_INTR_1_CTXNOTVALID_READ)) { + assert(recover); + } else { + assert(!recover); + } + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "%s branches=%s\n", __func__, + branches_str(branches, labels)); + } + return ret; +} + +int test_gv11b_pbdma_intr_descs(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_fifo *f = &g->fifo; + u32 intr_descs = (f->intr.pbdma.device_fatal_0 | + f->intr.pbdma.channel_fatal_0 | + f->intr.pbdma.restartable_0); + u32 channel_fatal_0 = gv11b_pbdma_channel_fatal_0_intr_descs(); + + assert(channel_fatal_0 != 0); + assert((intr_descs & channel_fatal_0) == channel_fatal_0); + + ret = UNIT_SUCCESS; +done: + return ret; + +} + +int test_gv11b_pbdma_get_fc(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + + assert(gv11b_pbdma_get_fc_pb_header() == + (pbdma_pb_header_method_zero_f() | + pbdma_pb_header_subchannel_zero_f() | + pbdma_pb_header_level_main_f() | + pbdma_pb_header_first_true_f() | + pbdma_pb_header_type_inc_f())); + + assert(gv11b_pbdma_get_fc_target() == + (pbdma_target_engine_sw_f() | + pbdma_target_eng_ctx_valid_true_f() | + pbdma_target_ce_ctx_valid_true_f())); + + ret = UNIT_SUCCESS; +done: + return ret; +} + +int test_gv11b_pbdma_set_channel_info_veid(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + u32 subctx_id; + + for (subctx_id = 0; subctx_id < 64; subctx_id ++) { + assert(gv11b_pbdma_set_channel_info_veid(subctx_id) == + pbdma_set_channel_info_veid_f(subctx_id)); + } + + ret = UNIT_SUCCESS; +done: + return ret; +} + +int test_gv11b_pbdma_config_userd_writeback_enable(struct unit_module *m, + struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + + assert(gv11b_pbdma_config_userd_writeback_enable() == + pbdma_config_userd_writeback_enable_f()); + + ret = UNIT_SUCCESS; +done: + return ret; +} + +struct unit_module_test nvgpu_pbdma_gv11b_tests[] = { + UNIT_TEST(init_support, test_fifo_init_support, NULL, 0), + UNIT_TEST(setup_hw, test_gv11b_pbdma_setup_hw, NULL, 0), + UNIT_TEST(intr_enable, test_gv11b_pbdma_intr_enable, NULL, 0), + UNIT_TEST(handle_intr_0, test_gv11b_pbdma_handle_intr_0, NULL, 0), + UNIT_TEST(handle_intr_1, test_gv11b_pbdma_handle_intr_1, NULL, 0), + UNIT_TEST(intr_descs, test_gv11b_pbdma_intr_descs, NULL, 0), + UNIT_TEST(get_fc, test_gv11b_pbdma_get_fc, NULL, 0), + UNIT_TEST(set_channel_info_veid, + test_gv11b_pbdma_set_channel_info_veid, NULL, 0), + UNIT_TEST(config_userd_writeback_enable, + test_gv11b_pbdma_config_userd_writeback_enable, NULL, 0), + UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0), +}; + +UNIT_MODULE(nvgpu_pbdma_gv11b, nvgpu_pbdma_gv11b_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h new file mode 100644 index 000000000..601363ea3 --- /dev/null +++ b/userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef UNIT_NVGPU_PBDMA_GV11B_H +#define UNIT_NVGPU_PBDMA_GV11B_H + +#include + +struct unit_module; +struct gk20a; + +/** @addtogroup SWUTS-fifo-pbdma-gv11b + * @{ + * + * Software Unit Test Specification for fifo/pbdma/gv11b + */ + +/** + * Test specification for: test_gv11b_pbdma_setup_hw + * + * Description: PBDMA H/W initialization. + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_setup_hw + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Get number of PBDMA. + * - Call gv11b_pbdma_setup_hw. + * - For each HW PBDMA id, check that PBDMA timeout is set to max. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_setup_hw(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_intr_enable + * + * Description: PBDMA interrupt enabling/disabling. + * + * Test Type: Feature based + * + * Targets: test_gv11b_pbdma_intr_enable + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Get number of PBDMAs + * - Check interrupt enable case: + * - Call gv11b_pbdma_intr_enable with enable = true. + * - Check that interrupts were cleared for all HW PDBMA (i.e. non-zero value + * written to pbdma_intr_0 and pbdma_intr_1). + * - Check that all intr_0 interrupts are enabled (i.e. pbdma_intr_en_0 + * written with content of pbdma_intr_stall_r). + * - Check that all intr_1 interrupts are enabled (i.e. pbdma_intr_en_1 + * written with content of pbdma_intr_stall_1, with + pbdma_intr_stall_1_hce_illegal_op_enabled_f cleared). + * - Check interrupt disable case: + * - Call gv11b_pbdma_intr_enable with enable = false. + * - Check that interrupts were disabled for all HW PDBMA (i.e. zero written + * to pbdma_intr_0 and pbdma_intr_1). + * - Check that interrupts were cleared for all HW PDBMA (i.e. non-zero value + * written to pbdma_intr_0 and pbdma_intr_1). + * + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_intr_enable(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_handle_intr_0 + * + * Description: Interrupt handling for pbdma_intr_0 + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_handle_intr_0 + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Set pbdma_intr_0 with a combination of the following interrupts: + * - clear_faulted_error: Check that recover is true and that method0 has + * been reset. + * - eng_reset: Check that recover is true. + * - Other interrupts are tested explicitly for gm20b_pbdma_handle_intr_0. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_handle_intr_0(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_handle_intr_1 + * + * Description: Interrupt handling for pbdma_intr_1 + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_handle_intr_1 + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Set pbdma_intr_1 variable (passed to the interrupt handling function) and + * pbdma_intr_1_r() register (using nvgpu_writel). + * - Call gv11b_pbdma_handle_intr_1 with pbdma_intr_1 variable. + * - Check that recover is true only when both pbdma_intr_1 variable and + * register are true. + * - Check that recover is false otherwise. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_handle_intr_1(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_intr_descs + * + * Description: Fatal channel interrupt mask + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_channel_fatal_0_intr_descs. + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Get mask of fatal channel interrupts with gv11b_pbdma_channel_fatal_0_intr_descs. + * - Check that g->fifo is configured to process those interrupts. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_intr_descs(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_get_fc + * + * Description: Get settings to program RAMFC. + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_get_fc_pb_header, gv11b_pbdma_get_fc_target + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Check that gv11b_pbdma_get_fc_pb_header() returns default for + * PB header (no method, no subch). + * - Check that gv11b_pbdma_get_fc_target() indicates that contexts + * are valid (CE and non-CE). + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_get_fc(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_set_channel_info_veid + * + * Description: PBDMA sub-context id (aka veid) + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_set_channel_info_veid + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - For each subctx_id (0..63), check that gv11b_pbdma_set_channel_info_veid + * returns veid as per HW manuals. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_set_channel_info_veid(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * Test specification for: test_gv11b_pbdma_config_userd_writeback_enable + * + * Description: USERD writeback enable + * + * Test Type: Feature based + * + * Targets: gv11b_pbdma_config_userd_writeback_enable + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Check that gv11b_pbdma_config_userd_writeback_enable() returns + * USER writeback enable as per HW manuals. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gv11b_pbdma_config_userd_writeback_enable(struct unit_module *m, + struct gk20a *g, void *args); + +/** + * @} + */ + +#endif /* UNIT_NVGPU_PBDMA_GV11B_H */