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gpu: nvgpu: vgpu: restructure event handling

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Take interrupts as one kind of event message, and make it
easier to add new kind of events.

JIRA VFND-3291
Bug 200257899

Change-Id: I83482293230c0aa10b05caf61e249a042bf6653c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1278396
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2016-12-28 14:44:59 -08:00
committed by mobile promotions
parent 48ce94f940
commit ecc3722aa1
2 changed files with 31 additions and 28 deletions
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53
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -1,7 +1,7 @@
/* /*
* Virtualized GPU * Virtualized GPU
* *
* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -102,12 +102,12 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
return 0; return 0;
} }
static void vgpu_handle_general_event(struct gk20a *g, static void vgpu_handle_channel_event(struct gk20a *g,
struct tegra_vgpu_general_event_info *info) struct tegra_vgpu_channel_event_info *info)
{ {
if (info->id >= g->fifo.num_channels || if (info->id >= g->fifo.num_channels ||
info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) { info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) {
gk20a_err(g->dev, "invalid general event"); gk20a_err(g->dev, "invalid channel event");
return; return;
} }
@@ -152,30 +152,33 @@ static int vgpu_intr_thread(void *dev_id)
break; break;
} }
if (msg->event == TEGRA_VGPU_EVENT_FECS_TRACE) { switch (msg->event) {
case TEGRA_VGPU_EVENT_INTR:
if (msg->unit == TEGRA_VGPU_INTR_GR)
vgpu_gr_isr(g, &msg->info.gr_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
vgpu_gr_nonstall_isr(g,
&msg->info.gr_nonstall_intr);
else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
vgpu_fifo_isr(g, &msg->info.fifo_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
vgpu_fifo_nonstall_isr(g,
&msg->info.fifo_nonstall_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
vgpu_ce2_nonstall_isr(g,
&msg->info.ce2_nonstall_intr);
break;
case TEGRA_VGPU_EVENT_FECS_TRACE:
vgpu_fecs_trace_data_update(g); vgpu_fecs_trace_data_update(g);
tegra_gr_comm_release(handle); break;
continue; case TEGRA_VGPU_EVENT_CHANNEL:
vgpu_handle_channel_event(g, &msg->info.channel_event);
break;
default:
gk20a_err(g->dev, "unknown event %u", msg->event);
break;
} }
if (msg->event == TEGRA_VGPU_EVENT_CHANNEL) {
vgpu_handle_general_event(g, &msg->info.general_event);
tegra_gr_comm_release(handle);
continue;
}
if (msg->unit == TEGRA_VGPU_INTR_GR)
vgpu_gr_isr(g, &msg->info.gr_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
vgpu_gr_nonstall_isr(g, &msg->info.gr_nonstall_intr);
else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
vgpu_fifo_isr(g, &msg->info.fifo_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
vgpu_fifo_nonstall_isr(g,
&msg->info.fifo_nonstall_intr);
else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
vgpu_ce2_nonstall_isr(g, &msg->info.ce2_nonstall_intr);
tegra_gr_comm_release(handle); tegra_gr_comm_release(handle);
} }

6
include/linux/tegra_vgpu.h
View File

@@ -1,7 +1,7 @@
/* /*
* Tegra GPU Virtualization Interfaces to Server * Tegra GPU Virtualization Interfaces to Server
* *
* Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved. * Copyright (c) 2014-2017, NVIDIA Corporation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -554,7 +554,7 @@ struct tegra_vgpu_fecs_trace_event_info {
u32 type; u32 type;
}; };
struct tegra_vgpu_general_event_info { struct tegra_vgpu_channel_event_info {
u32 event_id; u32 event_id;
u32 is_tsg; u32 is_tsg;
u32 id; /* channel id or tsg id */ u32 id; /* channel id or tsg id */
@@ -587,7 +587,7 @@ struct tegra_vgpu_intr_msg {
struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr;
struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr;
struct tegra_vgpu_fecs_trace_event_info fecs_trace; struct tegra_vgpu_fecs_trace_event_info fecs_trace;
struct tegra_vgpu_general_event_info general_event; struct tegra_vgpu_channel_event_info channel_event;
char padding[32]; char padding[32];
} info; } info;
}; };