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gpu: nvgpu: vgpu: restructure event handling
Take interrupts as one kind of event message, and make it easier to add new kind of events. JIRA VFND-3291 Bug 200257899 Change-Id: I83482293230c0aa10b05caf61e249a042bf6653c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1278396 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* Virtualized GPU
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -102,12 +102,12 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
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return 0;
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}
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static void vgpu_handle_general_event(struct gk20a *g,
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struct tegra_vgpu_general_event_info *info)
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static void vgpu_handle_channel_event(struct gk20a *g,
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struct tegra_vgpu_channel_event_info *info)
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{
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if (info->id >= g->fifo.num_channels ||
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info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) {
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gk20a_err(g->dev, "invalid general event");
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gk20a_err(g->dev, "invalid channel event");
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return;
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}
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@@ -152,30 +152,33 @@ static int vgpu_intr_thread(void *dev_id)
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break;
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}
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if (msg->event == TEGRA_VGPU_EVENT_FECS_TRACE) {
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switch (msg->event) {
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case TEGRA_VGPU_EVENT_INTR:
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if (msg->unit == TEGRA_VGPU_INTR_GR)
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vgpu_gr_isr(g, &msg->info.gr_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
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vgpu_gr_nonstall_isr(g,
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&msg->info.gr_nonstall_intr);
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else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
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vgpu_fifo_isr(g, &msg->info.fifo_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
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vgpu_fifo_nonstall_isr(g,
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&msg->info.fifo_nonstall_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
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vgpu_ce2_nonstall_isr(g,
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&msg->info.ce2_nonstall_intr);
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break;
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case TEGRA_VGPU_EVENT_FECS_TRACE:
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vgpu_fecs_trace_data_update(g);
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tegra_gr_comm_release(handle);
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continue;
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break;
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case TEGRA_VGPU_EVENT_CHANNEL:
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vgpu_handle_channel_event(g, &msg->info.channel_event);
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break;
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default:
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gk20a_err(g->dev, "unknown event %u", msg->event);
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break;
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}
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if (msg->event == TEGRA_VGPU_EVENT_CHANNEL) {
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vgpu_handle_general_event(g, &msg->info.general_event);
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tegra_gr_comm_release(handle);
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continue;
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}
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if (msg->unit == TEGRA_VGPU_INTR_GR)
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vgpu_gr_isr(g, &msg->info.gr_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)
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vgpu_gr_nonstall_isr(g, &msg->info.gr_nonstall_intr);
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else if (msg->unit == TEGRA_VGPU_INTR_FIFO)
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vgpu_fifo_isr(g, &msg->info.fifo_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO)
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vgpu_fifo_nonstall_isr(g,
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&msg->info.fifo_nonstall_intr);
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else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2)
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vgpu_ce2_nonstall_isr(g, &msg->info.ce2_nonstall_intr);
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tegra_gr_comm_release(handle);
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}
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@@ -1,7 +1,7 @@
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/*
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* Tegra GPU Virtualization Interfaces to Server
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*
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* Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2014-2017, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -554,7 +554,7 @@ struct tegra_vgpu_fecs_trace_event_info {
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u32 type;
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};
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struct tegra_vgpu_general_event_info {
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struct tegra_vgpu_channel_event_info {
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u32 event_id;
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u32 is_tsg;
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u32 id; /* channel id or tsg id */
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@@ -587,7 +587,7 @@ struct tegra_vgpu_intr_msg {
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struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr;
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struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr;
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struct tegra_vgpu_fecs_trace_event_info fecs_trace;
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struct tegra_vgpu_general_event_info general_event;
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struct tegra_vgpu_channel_event_info channel_event;
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char padding[32];
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} info;
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};
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