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gpu: nvgpu: Reorg falcon HAL initialization

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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
falcon sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ib1aaaa248b079bb591ccfada3382b689452de0e9
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514012
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Sunny He
2017-06-28 17:56:44 -07:00
committed by mobile promotions
parent 90d388ebf8
commit ecf67ebbf6
7 changed files with 20 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
View File

@@ -382,7 +382,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
gk20a_falcon_engine_dependency_ops(flcn);
}
static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
@@ -420,8 +420,3 @@ static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
nvgpu_log_info(g, "falcon 0x%x not supported on %s",
flcn->flcn_id, g->name);
}
void gk20a_falcon_init_hal(struct gpu_ops *gops)
{
gops->falcon.falcon_hal_sw_init = gk20a_falcon_hal_sw_init;
}

2
drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
View File

@@ -14,6 +14,6 @@
#define __FLCN_GK20A_H__
void gk20a_falcon_ops(struct nvgpu_falcon *flcn);
void gk20a_falcon_init_hal(struct gpu_ops *gops);
void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
#endif /* __FLCN_GK20A_H__ */

7
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -200,7 +200,10 @@ static const struct gpu_ops gm20b_ops = {
gr_gm20b_pg_gr_load_gating_prod,
},
.cde = {
.get_program_numbers = gm20b_cde_get_program_numbers
.get_program_numbers = gm20b_cde_get_program_numbers,
},
.falcon = {
.falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
},
.chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
.get_litter_value = gm20b_get_litter_value,
@@ -215,6 +218,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->ltc = gm20b_ops.ltc;
gops->clock_gating = gm20b_ops.clock_gating;
gops->cde = gm20b_ops.cde;
gops->falcon = gm20b_ops.falcon;
/* Lone functions */
gops->chip_init_gpu_characteristics =
@@ -259,7 +263,6 @@ int gm20b_init_hal(struct gk20a *g)
gm20b_init_ce2(gops);
gm20b_init_gr_ctx(gops);
gm20b_init_mm(gops);
gk20a_falcon_init_hal(gops);
gm20b_init_pmu_ops(gops);
gm20b_init_clk_ops(gops);
gm20b_init_regops(gops);

7
drivers/gpu/nvgpu/gp106/flcn_gp106.c
View File

@@ -40,7 +40,7 @@ static void gp106_falcon_ops(struct nvgpu_falcon *flcn)
gp106_falcon_engine_dependency_ops(flcn);
}
static void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
@@ -78,8 +78,3 @@ static void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
nvgpu_info(g, "falcon 0x%x not supported on %s",
flcn->flcn_id, g->name);
}
void gp106_falcon_init_hal(struct gpu_ops *gops)
{
gops->falcon.falcon_hal_sw_init = gp106_falcon_hal_sw_init;
}

8
drivers/gpu/nvgpu/gp106/flcn_gp106.h
View File

@@ -10,9 +10,9 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __FLCN_GK20A_H__
#define __FLCN_GK20A_H__
#ifndef __FLCN_GP106_H__
#define __FLCN_GP106_H__
void gp106_falcon_init_hal(struct gpu_ops *gops);
void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
#endif /* __FLCN_GK20A_H__ */
#endif /* __FLCN_GP106_H__ */

5
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -259,6 +259,9 @@ static const struct gpu_ops gp106_ops = {
.enable_shadow_rom = xve_enable_shadow_rom_gp106,
.disable_shadow_rom = xve_disable_shadow_rom_gp106,
},
.falcon = {
.falcon_hal_sw_init = gp106_falcon_hal_sw_init,
},
.get_litter_value = gp106_get_litter_value,
.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
.bios_init = gm206_bios_init,
@@ -275,6 +278,7 @@ int gp106_init_hal(struct gk20a *g)
gops->clock_gating = gp106_ops.clock_gating;
gops->cde = gp106_ops.cde;
gops->xve = gp106_ops.xve;
gops->falcon = gp106_ops.falcon;
/* Lone functions */
gops->get_litter_value = gp106_ops.get_litter_value;
@@ -295,7 +299,6 @@ int gp106_init_hal(struct gk20a *g)
gp10b_init_ce(gops);
gp106_init_gr_ctx(gops);
gp106_init_mm(gops);
gp106_falcon_init_hal(gops);
gp106_init_pmu_ops(gops);
gk20a_init_debug_ops(gops);
gk20a_init_dbg_session_ops(gops);

5
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -212,6 +212,9 @@ static const struct gpu_ops gp10b_ops = {
.need_scatter_buffer = gp10b_need_scatter_buffer,
.populate_scatter_buffer = gp10b_populate_scatter_buffer,
},
.falcon = {
.falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
},
.chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};
@@ -225,6 +228,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->ltc = gp10b_ops.ltc;
gops->clock_gating = gp10b_ops.clock_gating;
gops->cde = gp10b_ops.cde;
gops->falcon = gp10b_ops.falcon;
/* Lone Functions */
gops->chip_init_gpu_characteristics =
@@ -279,7 +283,6 @@ int gp10b_init_hal(struct gk20a *g)
gp10b_init_ce(gops);
gp10b_init_gr_ctx(gops);
gp10b_init_mm(gops);
gk20a_falcon_init_hal(gops);
gp10b_init_pmu_ops(gops);
gk20a_init_debug_ops(gops);
gk20a_init_dbg_session_ops(gops);