From ed4eb79ac15fa13512ca68b17f6cd007c5f99bd3 Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Thu, 20 Feb 2020 17:40:15 +0530 Subject: [PATCH] gpu: nvgpu: SWUD Lite updates Updated minor typo errors found during code inspection JIRA NVGPU-4785 JIRA NVGPU-4789 Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560 Reviewed-by: Mahantesh Kumbar Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/acr.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h | 19 +++++++++---------- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 2 +- 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h index 9831ec2e6..506b9f52b 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h @@ -36,7 +36,6 @@ void gv11b_setup_apertures(struct gk20a *g); bool gv11b_pmu_is_engine_in_reset(struct gk20a *g); void gv11b_pmu_engine_reset(struct gk20a *g, bool do_reset); u32 gv11b_pmu_falcon_base_addr(void); -void gv11b_secured_pmu_start(struct gk20a *g); bool gv11b_is_pmu_supported(struct gk20a *g); int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr); void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0); @@ -45,6 +44,7 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0); int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, u32 args_offset); void gv11b_pmu_setup_elpg(struct gk20a *g); +void gv11b_secured_pmu_start(struct gk20a *g); void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr); u32 gv11b_pmu_queue_head_r(u32 i); u32 gv11b_pmu_queue_head__size_1_v(void); diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr.h index c830df334..7526f325a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr.h @@ -173,7 +173,7 @@ struct nvgpu_acr; * + Allocate memory for ACR unit private struct #nvgpu_acr, return -ENOMEM upon * failure else continue to next step. * + Based on detected chip, init calls chip specific s/w init. For gv11b, - * nvgpu_gv11b_acr_sw_init is called to set. Static properties like + * nvgpu_gv11b_acr_sw_init is called to set static properties like * bootstrap_owner, supported LS Falcons & ops update. * + Struct #nvgpu_acr member gets set as below for gv11b, * + FALCON_ID_PMU for bootstrap_owner as ACR HS ucode runs on PMU engine diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h index a285dde53..80e0ed322 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h @@ -182,16 +182,6 @@ struct gops_pmu { */ void (*setup_apertures)(struct gk20a *g); - /** - * @brief Start PMU falcon CPU in secure mode. - * - * @param g [in] The GPU driver struct. - * - * Start PMU falcon CPU in secure mode by writing true to - * CPUCTL_ALIAS. - */ - void (*secured_pmu_start)(struct gk20a *g); - /** * @brief Clears the PMU BAR0 error status. * @@ -349,6 +339,15 @@ struct gops_pmu { void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu); void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu); void (*dump_secure_fuses)(struct gk20a *g); + /** + * @brief Start PMU falcon CPU in secure mode. + * + * @param g [in] The GPU driver struct. + * + * Start PMU falcon CPU in secure mode by writing true to + * CPUCTL_ALIAS. + */ + void (*secured_pmu_start)(struct gk20a *g); /** * @brief Setup DMA transfer base address. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index e53361f1f..204cd7f77 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -370,7 +370,7 @@ void nvgpu_pmu_enable_irq(struct gk20a *g, bool enable); * * @param g [in] The GPU driver struct. * - * Dose the PMU Engine reset to bring into good known state. The reset sequence + * Does the PMU Engine reset to bring into good known state. The reset sequence * also configures PMU Engine clock gating & interrupts if interrupt support is * enabled. *