diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index 8b36394d8..c1b8d5e1b 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -49,15 +49,19 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
 {
 	struct pmu_cmd cmd;
 	struct pmu_msg msg;
-	struct pmu_payload payload = { {0} };
+	struct pmu_payload payload;
 	u32 status;
 	u32 seqdesc;
-	struct nv_pmu_clk_rpc rpccall = {0};
-	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_rpc rpccall;
+	struct clkrpc_pmucmdhandler_params handler;
 	struct nv_pmu_clk_load *clkload;
 	struct clk_freq_controllers *pclk_freq_controllers;
 	struct ctrl_boardobjgrp_mask_e32 *load_mask;
 
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
 	pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
 	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
 	clkload = &rpccall.params.clk_load;
@@ -120,13 +124,17 @@ u32 clk_pmu_vin_load(struct gk20a *g)
 {
 	struct pmu_cmd cmd;
 	struct pmu_msg msg;
-	struct pmu_payload payload = { {0} };
+	struct pmu_payload payload;
 	u32 status;
 	u32 seqdesc;
-	struct nv_pmu_clk_rpc rpccall = {0};
-	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_rpc rpccall;
+	struct clkrpc_pmucmdhandler_params handler;
 	struct nv_pmu_clk_load *clkload;
 
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
 	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
 	clkload = &rpccall.params.clk_load;
 	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
@@ -179,13 +187,17 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
 {
 	struct pmu_cmd cmd;
 	struct pmu_msg msg;
-	struct pmu_payload payload = { {0} };
+	struct pmu_payload payload;
 	u32 status;
 	u32 seqdesc;
-	struct nv_pmu_clk_rpc rpccall = {0};
-	struct clkrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_clk_rpc rpccall;
+	struct clkrpc_pmucmdhandler_params handler;
 	struct nv_pmu_clk_vf_change_inject *vfchange;
 
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
 	if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
 		(setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c
index c784bdb4d..84ce7371a 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/clk/clk_domain.c
@@ -31,7 +31,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g,
 static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
 	*board_obj_ptr,	struct nv_pmu_boardobj *ppmudata);
 
-const struct vbios_clocks_table_1x_hal_clock_entry vbiosclktbl1xhalentry[] = {
+static const struct vbios_clocks_table_1x_hal_clock_entry
+		vbiosclktbl1xhalentry[] = {
 	{ clkwhich_gpc2clk,    true,  },
 	{ clkwhich_xbar2clk,   true,  },
 	{ clkwhich_mclk,       false, },
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
index 61c8b81b0..632d7b35b 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
@@ -144,7 +144,8 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g,
 	return status;
 }
 
-struct clk_freq_controller *clk_clk_freq_controller_construct(struct gk20a *g,
+static struct clk_freq_controller *clk_clk_freq_controller_construct(
+	struct gk20a *g,
 	void *pargs)
 {
 	struct boardobj *board_obj_ptr = NULL;
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c
index 690f86814..cf04c98c6 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.c
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.c
@@ -2262,7 +2262,7 @@ fail_mclk_mutex:
 int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
 {
 	struct clk_mclk_state *mclk;
-	struct pmu_payload payload = { {0} };
+	struct pmu_payload payload;
 	struct nv_pmu_seq_cmd cmd;
 	struct nv_pmu_seq_cmd_run_script *pseq_cmd;
 	u32 seqdesc;
@@ -2277,6 +2277,8 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
 
 	gk20a_dbg_info("");
 
+	memset(&payload, 0, sizeof(struct pmu_payload));
+
 	mclk = &g->clk_pmu.clk_mclk;
 
 	nvgpu_mutex_acquire(&mclk->mclk_lock);
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c
index 871ff7530..9adcadb6b 100644
--- a/drivers/gpu/nvgpu/perf/perf.c
+++ b/drivers/gpu/nvgpu/perf/perf.c
@@ -61,11 +61,15 @@ u32 perf_pmu_vfe_load(struct gk20a *g)
 {
 	struct pmu_cmd cmd;
 	struct pmu_msg msg;
-	struct pmu_payload payload = { {0} };
+	struct pmu_payload payload;
 	u32 status;
 	u32 seqdesc;
-	struct nv_pmu_perf_rpc rpccall = {0};
-	struct perfrpc_pmucmdhandler_params handler = {0};
+	struct nv_pmu_perf_rpc rpccall;
+	struct perfrpc_pmucmdhandler_params handler;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_perf_rpc));
+	memset(&handler, 0, sizeof(struct perfrpc_pmucmdhandler_params));
 
 	/*register call back for future VFE updates*/
 	g->ops.perf.handle_pmu_perf_event = pmu_handle_perf_event;
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c
index 996929c23..c1f87c254 100644
--- a/drivers/gpu/nvgpu/perf/vfe_var.c
+++ b/drivers/gpu/nvgpu/perf/vfe_var.c
@@ -161,7 +161,7 @@ u32 vfe_var_pmu_setup(struct gk20a *g)
 	return status;
 }
 
-u32 dev_init_get_vfield_info(struct gk20a *g,
+static u32 dev_init_get_vfield_info(struct gk20a *g,
 	struct vfe_var_single_sensed_fuse *pvfevar)
 {
 	u8 *vfieldtableptr = NULL;
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index d09becd6c..b30dccca9 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -81,12 +81,16 @@ static u32 pmgr_pmu_set_object(struct gk20a *g,
 		u16 fb_size,
 		void *pobj)
 {
-	struct pmu_cmd cmd = { {0} };
-	struct pmu_payload payload = { {0} };
+	struct pmu_cmd cmd;
+	struct pmu_payload payload;
 	struct nv_pmu_pmgr_cmd_set_object *pcmd;
 	u32 status;
 	u32 seqdesc;
-	struct pmgr_pmucmdhandler_params handlerparams = {0};
+	struct pmgr_pmucmdhandler_params handlerparams;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	memset(&handlerparams, 0, sizeof(struct pmgr_pmucmdhandler_params));
 
 	cmd.hdr.unit_id = PMU_UNIT_PMGR;
 	cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_set_object) +
@@ -360,12 +364,16 @@ u32 pmgr_pmu_pwr_devices_query_blocking(
 		u32 pwr_dev_mask,
 		struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload)
 {
-	struct pmu_cmd cmd = { {0} };
-	struct pmu_payload payload = { {0} };
+	struct pmu_cmd cmd;
+	struct pmu_payload payload;
 	struct nv_pmu_pmgr_cmd_pwr_devices_query *pcmd;
 	u32 status;
 	u32 seqdesc;
-	struct pmgr_pmucmdhandler_params handlerparams = {0};
+	struct pmgr_pmucmdhandler_params handlerparams;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	memset(&handlerparams, 0, sizeof(struct pmgr_pmucmdhandler_params));
 
 	cmd.hdr.unit_id = PMU_UNIT_PMGR;
 	cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_pwr_devices_query) +
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c
index 3d80eff34..84e9871a0 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.c
@@ -115,11 +115,17 @@ exit:
 static u32 therm_set_warn_temp_limit(struct gk20a *g)
 {
 	u32 seqdesc = 0;
-	struct pmu_cmd cmd = { {0} };
-	struct pmu_msg msg = { {0} };
-	struct pmu_payload payload = { {0} };
-	struct nv_pmu_therm_rpc rpccall = {0};
-	struct therm_pmucmdhandler_params handlerparams = {0};
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload;
+	struct nv_pmu_therm_rpc rpccall;
+	struct therm_pmucmdhandler_params handlerparams;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	memset(&msg, 0, sizeof(struct pmu_msg));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc));
+	memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params));
 
 	rpccall.function = NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET;
 	rpccall.params.slct_event_temp_th_set.event_id =
@@ -178,11 +184,17 @@ static u32 therm_enable_slct_notification_request(struct gk20a *g)
 static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g)
 {
 	u32 seqdesc = 0;
-	struct pmu_cmd cmd = { {0} };
-	struct pmu_msg msg = { {0} };
-	struct pmu_payload payload = { {0} };
-	struct nv_pmu_therm_rpc rpccall = {0};
-	struct therm_pmucmdhandler_params handlerparams = {0};
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload;
+	struct nv_pmu_therm_rpc rpccall;
+	struct therm_pmucmdhandler_params handlerparams;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	memset(&msg, 0, sizeof(struct pmu_msg));
+	memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc));
+	memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params));
 
 	rpccall.function = NV_PMU_THERM_RPC_ID_SLCT;
 	rpccall.params.slct.mask_enabled =
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
index dd2a0a635..871afce51 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.c
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -51,12 +51,17 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 static u32 volt_pmu_rpc_execute(struct gk20a *g,
 	struct nv_pmu_volt_rpc *prpc_call)
 {
-	struct pmu_cmd cmd = { { 0 } };
-	struct pmu_msg msg = { { 0 } };
-	struct pmu_payload payload = { { 0 } };
+	struct pmu_cmd cmd;
+	struct pmu_msg msg;
+	struct pmu_payload payload;
 	u32 status = 0;
 	u32 seqdesc;
-	struct volt_rpc_pmucmdhandler_params handler = {0};
+	struct volt_rpc_pmucmdhandler_params handler;
+
+	memset(&payload, 0, sizeof(struct pmu_payload));
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	memset(&msg, 0, sizeof(struct pmu_msg));
+	memset(&handler, 0, sizeof(struct volt_rpc_pmucmdhandler_params));
 
 	cmd.hdr.unit_id = PMU_UNIT_VOLT;
 	cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) +