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gpu: nvgpu: gr: move init_ctxsw_ucode to common falcon
Move functions related to init_ctxsw_ucode to common falcon from gr_gk20a.c. Modified code to call this new function and modified function names in common falcon to reflect new re-org. JIRA NVGPU-1881 Change-Id: I389f5c902bfbec17cdb4b16840a5ba66f6b1e331 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081331 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
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mobile promotions
mobile promotions
parent
b82f2075ae
commit
ee06ecfd2e
@@ -51,6 +51,7 @@
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#include <nvgpu/gr/ctx.h>
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#include <nvgpu/gr/zbc.h>
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#include <nvgpu/gr/gr.h>
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#include <nvgpu/gr/gr_falcon.h>
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#include <nvgpu/gr/zcull.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/gr/fecs_trace.h>
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@@ -1109,172 +1110,6 @@ static void gr_gk20a_start_falcon_ucode(struct gk20a *g)
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nvgpu_log_fn(g, "done");
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}
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static int gr_gk20a_init_ctxsw_ucode_vaspace(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->pmu.vm;
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struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
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int err;
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err = g->ops.mm.alloc_inst_block(g, &ucode_info->inst_blk_desc);
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if (err != 0) {
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return err;
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}
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g->ops.mm.init_inst_block(&ucode_info->inst_blk_desc, vm, 0);
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/* Map ucode surface to GMMU */
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ucode_info->surface_desc.gpu_va = nvgpu_gmmu_map(vm,
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&ucode_info->surface_desc,
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ucode_info->surface_desc.size,
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0, /* flags */
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gk20a_mem_flag_read_only,
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false,
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ucode_info->surface_desc.aperture);
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if (ucode_info->surface_desc.gpu_va == 0ULL) {
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nvgpu_err(g, "failed to update gmmu ptes");
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return -ENOMEM;
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}
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return 0;
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}
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static void gr_gk20a_init_ctxsw_ucode_segment(
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struct gk20a_ctxsw_ucode_segment *p_seg, u32 *offset, u32 size)
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{
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p_seg->offset = *offset;
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p_seg->size = size;
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*offset = ALIGN(*offset + size, BLK_SIZE);
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}
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static void gr_gk20a_init_ctxsw_ucode_segments(
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struct gk20a_ctxsw_ucode_segments *segments, u32 *offset,
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struct gk20a_ctxsw_bootloader_desc *bootdesc,
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u32 code_size, u32 data_size)
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{
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u32 boot_size = ALIGN(bootdesc->size, sizeof(u32));
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segments->boot_entry = bootdesc->entry_point;
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segments->boot_imem_offset = bootdesc->imem_offset;
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gr_gk20a_init_ctxsw_ucode_segment(&segments->boot, offset, boot_size);
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gr_gk20a_init_ctxsw_ucode_segment(&segments->code, offset, code_size);
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gr_gk20a_init_ctxsw_ucode_segment(&segments->data, offset, data_size);
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}
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static int gr_gk20a_copy_ctxsw_ucode_segments(
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struct gk20a *g,
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struct nvgpu_mem *dst,
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struct gk20a_ctxsw_ucode_segments *segments,
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u32 *bootimage,
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u32 *code, u32 *data)
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{
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unsigned int i;
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nvgpu_mem_wr_n(g, dst, segments->boot.offset, bootimage,
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segments->boot.size);
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nvgpu_mem_wr_n(g, dst, segments->code.offset, code,
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segments->code.size);
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nvgpu_mem_wr_n(g, dst, segments->data.offset, data,
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segments->data.size);
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/* compute a "checksum" for the boot binary to detect its version */
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segments->boot_signature = 0;
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for (i = 0; i < segments->boot.size / sizeof(u32); i++) {
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segments->boot_signature += bootimage[i];
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}
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return 0;
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}
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int gr_gk20a_init_ctxsw_ucode(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->pmu.vm;
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struct gk20a_ctxsw_bootloader_desc *fecs_boot_desc;
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struct gk20a_ctxsw_bootloader_desc *gpccs_boot_desc;
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struct nvgpu_firmware *fecs_fw;
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struct nvgpu_firmware *gpccs_fw;
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u32 *fecs_boot_image;
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u32 *gpccs_boot_image;
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struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
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u32 ucode_size;
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int err = 0;
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fecs_fw = nvgpu_request_firmware(g, GK20A_FECS_UCODE_IMAGE, 0);
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if (fecs_fw == NULL) {
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nvgpu_err(g, "failed to load fecs ucode!!");
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return -ENOENT;
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}
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fecs_boot_desc = (void *)fecs_fw->data;
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fecs_boot_image = (void *)(fecs_fw->data +
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sizeof(struct gk20a_ctxsw_bootloader_desc));
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gpccs_fw = nvgpu_request_firmware(g, GK20A_GPCCS_UCODE_IMAGE, 0);
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if (gpccs_fw == NULL) {
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nvgpu_release_firmware(g, fecs_fw);
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nvgpu_err(g, "failed to load gpccs ucode!!");
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return -ENOENT;
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}
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gpccs_boot_desc = (void *)gpccs_fw->data;
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gpccs_boot_image = (void *)(gpccs_fw->data +
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sizeof(struct gk20a_ctxsw_bootloader_desc));
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ucode_size = 0;
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gr_gk20a_init_ctxsw_ucode_segments(&ucode_info->fecs, &ucode_size,
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fecs_boot_desc,
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g->netlist_vars->ucode.fecs.inst.count * (u32)sizeof(u32),
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g->netlist_vars->ucode.fecs.data.count * (u32)sizeof(u32));
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gr_gk20a_init_ctxsw_ucode_segments(&ucode_info->gpccs, &ucode_size,
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gpccs_boot_desc,
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g->netlist_vars->ucode.gpccs.inst.count * (u32)sizeof(u32),
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g->netlist_vars->ucode.gpccs.data.count * (u32)sizeof(u32));
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err = nvgpu_dma_alloc_sys(g, ucode_size, &ucode_info->surface_desc);
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if (err != 0) {
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goto clean_up;
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}
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gr_gk20a_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
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&ucode_info->fecs,
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fecs_boot_image,
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g->netlist_vars->ucode.fecs.inst.l,
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g->netlist_vars->ucode.fecs.data.l);
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nvgpu_release_firmware(g, fecs_fw);
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fecs_fw = NULL;
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gr_gk20a_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
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&ucode_info->gpccs,
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gpccs_boot_image,
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g->netlist_vars->ucode.gpccs.inst.l,
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g->netlist_vars->ucode.gpccs.data.l);
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nvgpu_release_firmware(g, gpccs_fw);
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gpccs_fw = NULL;
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err = gr_gk20a_init_ctxsw_ucode_vaspace(g);
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if (err != 0) {
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goto clean_up;
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}
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return 0;
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clean_up:
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if (ucode_info->surface_desc.gpu_va != 0ULL) {
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nvgpu_gmmu_unmap(vm, &ucode_info->surface_desc,
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ucode_info->surface_desc.gpu_va);
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}
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nvgpu_dma_free(g, &ucode_info->surface_desc);
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nvgpu_release_firmware(g, gpccs_fw);
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gpccs_fw = NULL;
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nvgpu_release_firmware(g, fecs_fw);
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fecs_fw = NULL;
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return err;
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}
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static void gr_gk20a_wait_for_fecs_arb_idle(struct gk20a *g)
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{
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int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT;
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@@ -1528,7 +1363,7 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g)
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gr_gk20a_start_falcon_ucode(g);
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} else {
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if (!g->gr.skip_ucode_init) {
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err = gr_gk20a_init_ctxsw_ucode(g);
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err = nvgpu_gr_falcon_init_ctxsw_ucode(g);
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if (err != 0) {
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return err;
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@@ -351,7 +351,6 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
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void gk20a_gr_set_shader_exceptions(struct gk20a *g, u32 data);
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void gr_gk20a_enable_hww_exceptions(struct gk20a *g);
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int gr_gk20a_init_ctxsw_ucode(struct gk20a *g);
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int gr_gk20a_load_ctxsw_ucode(struct gk20a *g);
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void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g);
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void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base,
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