From ee0a987dfde9a197b90d65ba2c85b148597d42e6 Mon Sep 17 00:00:00 2001 From: Karl Ding Date: Thu, 11 Oct 2018 15:41:59 -0700 Subject: [PATCH] gpu: nvgpu: vgpu: properly set dma mask Properly set the dma_mask and coherent_dma_mask for vgpu instead of using the default 32-bit mask. This fixes the dma_capable check that was previously failing. Bug 2412352 Change-Id: If1d5d74333f86855f8041cc199a04b4b8eb521b5 Signed-off-by: Karl Ding Reviewed-on: https://git-master.nvidia.com/r/1924967 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das Reviewed-by: Alex Waterman Reviewed-by: Nirav Patel Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 4 ++++ drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 0304bccbe..fa060847d 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -16,6 +16,8 @@ #include +#include + #include #include @@ -100,4 +102,6 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = { /* power management callbacks */ .suspend = vgpu_tegra_suspend, .resume = vgpu_tegra_resume, + + .dma_mask = DMA_BIT_MASK(36), }; diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c index aa2fa998e..d5c6f3d4c 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c @@ -453,6 +453,16 @@ int vgpu_probe(struct platform_device *pdev) dev->dma_parms = &l->dma_parms; dma_set_max_seg_size(dev, UINT_MAX); + /* + * A default of 16GB is the largest supported DMA size that is + * acceptable to all currently supported Tegra SoCs. + */ + if (!platform->dma_mask) + platform->dma_mask = DMA_BIT_MASK(34); + + dma_set_mask(dev, platform->dma_mask); + dma_set_coherent_mask(dev, platform->dma_mask); + gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT; gk20a->timeouts_disabled_by_user = false; nvgpu_atomic_set(&gk20a->timeouts_disabled_refcount, 0);