From ef1fb41e54893e37f649877b2b19fea705e7c08c Mon Sep 17 00:00:00 2001 From: Divya Date: Wed, 3 May 2023 15:36:08 +0000 Subject: [PATCH] gpu: nvgpu: add pmu hals to resolve mismatch Add the following HALs to avoid the duplication of code for future chips: - set_mailbox1 - get_ecc_address - get_ecc_status - set_ecc_status JIRA NVGPU-9758 Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb Signed-off-by: Divya Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 1 + drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 4 +++ drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 4 +++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 4 +++ drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c | 6 ++--- drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h | 1 + drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c | 5 ++++ drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c | 4 +-- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h | 5 +++- drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c | 30 +++++++++++++++------- drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h | 4 +++ 12 files changed, 54 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index ff8ecf5bc..129cae6c2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1359,6 +1359,7 @@ static const struct gops_pmu ga100_ops_pmu = { .pmu_get_queue_head = tu104_pmu_queue_head_r, .pmu_mutex_release = gk20a_pmu_mutex_release, .pmu_is_interrupted = gk20a_pmu_is_interrupted, + .set_mailbox1 = gk20a_pmu_set_mailbox1, .get_irqstat = gk20a_pmu_get_irqstat, .set_irqsclr = gk20a_pmu_set_irqsclr, .set_irqsset = gk20a_pmu_set_irqsset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 63c009230..977dba790 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1414,6 +1414,10 @@ static const struct gops_pmu ga10b_ops_pmu = { .get_irqmask = ga10b_pmu_get_irqmask, .pmu_isr = gk20a_pmu_isr, .handle_ext_irq = ga10b_pmu_handle_ext_irq, + .set_mailbox1 = gk20a_pmu_set_mailbox1, + .get_ecc_address = gv11b_pmu_get_ecc_address, + .get_ecc_status = gv11b_pmu_get_ecc_status, + .set_ecc_status = gv11b_pmu_set_ecc_status, .get_irqstat = gk20a_pmu_get_irqstat, .set_irqsclr = gk20a_pmu_set_irqsclr, .set_irqsset = gk20a_pmu_set_irqsset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 139d9ede8..11f8cac9e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -860,6 +860,7 @@ static const struct gops_pmu gm20b_ops_pmu = { .pmu_mutex_release = gk20a_pmu_mutex_release, .pmu_is_interrupted = gk20a_pmu_is_interrupted, .get_irqmask = gk20a_pmu_get_irqmask, + .set_mailbox1 = gk20a_pmu_set_mailbox1, .get_irqstat = gk20a_pmu_get_irqstat, .set_irqsclr = gk20a_pmu_set_irqsclr, .set_irqsset = gk20a_pmu_set_irqsset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 3e4a255e2..f28e4e335 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1173,6 +1173,10 @@ static const struct gops_pmu gv11b_ops_pmu = { .pmu_enable_irq = gv11b_pmu_enable_irq, .get_irqdest = gv11b_pmu_get_irqdest, .get_irqmask = gk20a_pmu_get_irqmask, + .set_mailbox1 = gk20a_pmu_set_mailbox1, + .get_ecc_address = gv11b_pmu_get_ecc_address, + .get_ecc_status = gv11b_pmu_get_ecc_status, + .set_ecc_status = gv11b_pmu_set_ecc_status, .get_irqstat = gk20a_pmu_get_irqstat, .set_irqsclr = gk20a_pmu_set_irqsclr, .set_irqsset = gk20a_pmu_set_irqsset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index b8eb836a6..b5ca00bc2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1236,6 +1236,10 @@ static const struct gops_pmu tu104_ops_pmu = { .pmu_mutex_release = gk20a_pmu_mutex_release, .pmu_is_interrupted = gk20a_pmu_is_interrupted, .get_irqmask = gk20a_pmu_get_irqmask, + .set_mailbox1 = gk20a_pmu_set_mailbox1, + .get_ecc_address = gv11b_pmu_get_ecc_address, + .get_ecc_status = gv11b_pmu_get_ecc_status, + .set_ecc_status = gv11b_pmu_set_ecc_status, .get_irqstat = gk20a_pmu_get_irqstat, .set_irqsclr = gk20a_pmu_set_irqsclr, .set_irqsset = gk20a_pmu_set_irqsset, diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c index 54dd6dc2c..f1d8aaca5 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -437,7 +437,7 @@ static int ga10b_pmu_handle_ecc(struct gk20a *g) int ret = 0; u32 ecc_status = 0; - ecc_status = nvgpu_readl(g, pwr_pmu_falcon_ecc_status_r()); + ecc_status = g->ops.pmu.get_ecc_status(g); if ((ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) { @@ -481,7 +481,7 @@ static int ga10b_pmu_handle_ecc(struct gk20a *g) if (ret != 0) { nvgpu_err(g, "ecc_addr(0x%x)", - nvgpu_readl(g, pwr_pmu_falcon_ecc_address_r())); + g->ops.pmu.get_ecc_address(g)); } return ret; diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h index 5a2308a64..3cf50a0d5 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h @@ -34,6 +34,7 @@ struct pmu_mutexes; void gk20a_pmu_isr(struct gk20a *g); u32 gk20a_pmu_get_irqmask(struct gk20a *g); +void gk20a_pmu_set_mailbox1(struct gk20a *g, u32 val); u32 gk20a_pmu_get_irqstat(struct gk20a *g); void gk20a_pmu_set_irqsclr(struct gk20a *g, u32 intr); void gk20a_pmu_set_irqsset(struct gk20a *g, u32 intr); diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c index dc32671cb..76dcb4e3e 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c @@ -38,6 +38,11 @@ u32 gk20a_pmu_get_irqmask(struct gk20a *g) return mask; } +void gk20a_pmu_set_mailbox1(struct gk20a *g, u32 val) +{ + nvgpu_writel(g, pwr_falcon_mailbox1_r(), val); +} + u32 gk20a_pmu_get_irqstat(struct gk20a *g) { return nvgpu_readl(g, pwr_falcon_irqstat_r()); diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c index a31070589..d545e2972 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gm20b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -194,7 +194,7 @@ void gm20b_pmu_flcn_setup_boot_config(struct gk20a *g) } /* Clearing mailbox register used to reflect capabilities */ - gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); + g->ops.pmu.set_mailbox1(g, 0); /* enable the context interface */ gk20a_writel(g, pwr_falcon_itfen_r(), diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h index 17bc2e6ff..7de2cea59 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,6 +38,9 @@ void gv11b_pmu_engine_reset(struct gk20a *g, bool do_reset); u32 gv11b_pmu_falcon_base_addr(void); bool gv11b_is_pmu_supported(struct gk20a *g); void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0); +u32 gv11b_pmu_get_ecc_address(struct gk20a *g); +u32 gv11b_pmu_get_ecc_status(struct gk20a *g); +void gv11b_pmu_set_ecc_status(struct gk20a *g, u32 val); #ifdef CONFIG_NVGPU_LS_PMU int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu, diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c index 9119c9d97..ea3b01369 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c @@ -81,6 +81,21 @@ static u32 pmu_bar0_hosterr_etype(u32 val) PMU_BAR0_WRITE_HOSTERR : PMU_BAR0_READ_HOSTERR; } +u32 gv11b_pmu_get_ecc_address(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_falcon_ecc_address_r()); +} + +u32 gv11b_pmu_get_ecc_status(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_falcon_ecc_status_r()); +} + +void gv11b_pmu_set_ecc_status(struct gk20a *g, u32 val) +{ + nvgpu_writel(g, pwr_pmu_falcon_ecc_status_r(), val); +} + int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, u32 *etype) { @@ -168,8 +183,8 @@ bool gv11b_pmu_validate_mem_integrity(struct gk20a *g) { u32 ecc_status, ecc_addr; - ecc_status = nvgpu_readl(g, pwr_pmu_falcon_ecc_status_r()); - ecc_addr = nvgpu_readl(g, pwr_pmu_falcon_ecc_address_r()); + ecc_status = g->ops.pmu.get_ecc_status(g); + ecc_addr = g->ops.pmu.get_ecc_address(g); return ((gv11b_pmu_correct_ecc(g, ecc_status, ecc_addr) == 0) ? true : false); @@ -195,7 +210,7 @@ void gv11b_pmu_flcn_setup_boot_config(struct gk20a *g) } /* Clearing mailbox register used to reflect capabilities */ - nvgpu_writel(g, pwr_falcon_mailbox1_r(), PWR_FALCON_MAILBOX1_DATA_INIT); + g->ops.pmu.set_mailbox1(g, PWR_FALCON_MAILBOX1_DATA_INIT); /* enable the context interface */ nvgpu_writel(g, pwr_falcon_itfen_r(), @@ -342,10 +357,8 @@ static void gv11b_pmu_handle_ecc_irq(struct gk20a *g) return; } - ecc_status = nvgpu_readl(g, - pwr_pmu_falcon_ecc_status_r()); - ecc_addr = nvgpu_readl(g, - pwr_pmu_falcon_ecc_address_r()); + ecc_status = g->ops.pmu.get_ecc_status(g); + ecc_addr = g->ops.pmu.get_ecc_address(g); corrected_cnt = nvgpu_readl(g, pwr_pmu_falcon_ecc_corrected_err_count_r()); uncorrected_cnt = nvgpu_readl(g, @@ -374,8 +387,7 @@ static void gv11b_pmu_handle_ecc_irq(struct gk20a *g) pwr_pmu_falcon_ecc_uncorrected_err_count_r(), 0); } - nvgpu_writel(g, pwr_pmu_falcon_ecc_status_r(), - pwr_pmu_falcon_ecc_status_reset_task_f()); + g->ops.pmu.set_ecc_status(g, pwr_pmu_falcon_ecc_status_reset_task_f()); /* update counters per slice */ if (corrected_overflow != 0U) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h index 20bc58ae0..477f4ad91 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h @@ -473,6 +473,10 @@ struct gops_pmu { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ void (*handle_swgen1_irq)(struct gk20a *g, u32 intr); u32 (*get_irqmask)(struct gk20a *g); + void (*set_mailbox1)(struct gk20a *g, u32 val); + u32 (*get_ecc_address)(struct gk20a *g); + u32 (*get_ecc_status)(struct gk20a *g); + void (*set_ecc_status)(struct gk20a *g, u32 val); u32 (*get_irqstat)(struct gk20a *g); void (*set_irqsclr)(struct gk20a *g, u32 intr); void (*set_irqsset)(struct gk20a *g, u32 intr);