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gpu: nvgpu: Fix MISRA rule 15.6 violations

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MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.

JIRA NVGPU-775

Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan Madhavan
2018-10-17 11:43:03 +05:30
committed by mobile promotions
parent 482d7e7ca2
commit ef5fdac7a6
21 changed files with 122 additions and 63 deletions
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6
drivers/gpu/nvgpu/common/ce2.c
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@@ -65,8 +65,9 @@ int gk20a_ce_execute_ops(struct gk20a *g,
struct nvgpu_channel_fence fence = {0, 0};
struct gk20a_fence *ce_cmd_buf_fence_out = NULL;
if (!ce_app->initialised ||ce_app->app_state != NVGPU_CE_ACTIVE)
if (!ce_app->initialised || ce_app->app_state != NVGPU_CE_ACTIVE) {
goto end;
}
nvgpu_mutex_acquire(&ce_app->app_mutex);
@@ -108,8 +109,9 @@ int gk20a_ce_execute_ops(struct gk20a *g,
gk20a_fence_put(*prev_post_fence);
*prev_post_fence = NULL;
if (ret != 0)
if (ret != 0) {
goto noop;
}
}
cmd_buf_gpu_va = (ce_ctx->cmd_buf_mem.gpu_va + (u64)(cmd_buf_read_offset *sizeof(u32)));