gpu: nvgpu: Fix MISRA rule 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.

JIRA NVGPU-775

Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan Madhavan
2018-10-17 11:43:03 +05:30
committed by mobile promotions
parent 482d7e7ca2
commit ef5fdac7a6
21 changed files with 122 additions and 63 deletions

View File

@@ -282,8 +282,9 @@ int gk20a_finalize_poweron(struct gk20a *g)
nvgpu_mutex_acquire(&g->tpc_pg_lock);
if (g->can_tpc_powergate) {
if (g->ops.gr.powergate_tpc != NULL)
if (g->ops.gr.powergate_tpc != NULL) {
g->ops.gr.powergate_tpc(g);
}
}
err = gk20a_enable_gr_hw(g);