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gpu: nvgpu: fix pmu->mscg_stat optimization issue

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- with help of WRITE_ONCE() & ACCESS_ONCE()
  make sure variable pmu->mscg_stat read/write goes through
  without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
  to support backward compatibility

issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat

JIRA DNVGPU-71

Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-11-14 11:27:38 +05:30
committed by mobile promotions
parent 157ff622f3
commit efe0758081
4 changed files with 29 additions and 11 deletions
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8
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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@@ -3388,7 +3388,9 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) {
pmu->initialized = true;
pmu->pmu_state = PMU_STATE_STARTED;
pmu->mscg_stat = PMU_MSCG_DISABLED;
WRITE_ONCE(pmu->mscg_stat, PMU_MSCG_DISABLED);
/* make status visible */
smp_mb();
} else {
pmu->pmu_state = PMU_STATE_ELPG_BOOTED;
schedule_work(&pmu->pg_init);
@@ -4849,7 +4851,7 @@ int gk20a_pmu_enable_elpg(struct gk20a *g)
pg_engine_id++) {
if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS &&
pmu->mscg_stat == PMU_MSCG_DISABLED)
ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED)
continue;
if (BIT(pg_engine_id) & pg_engine_id_list)
@@ -4925,7 +4927,7 @@ int gk20a_pmu_disable_elpg(struct gk20a *g)
pg_engine_id++) {
if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS &&
pmu->mscg_stat == PMU_MSCG_DISABLED)
ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED)
continue;
if (BIT(pg_engine_id) & pg_engine_id_list) {