gpu: nvgpu: Reading Vmin and Volt_rail get status

Changes:
1) volt_rail_boardobj_grp_get_status function implemented.
2) nvgpu_volt_get_vmin_tu10x function implemented.
3) Only Vmin is updated into boardobjs.

Bug 200454682
Bug 2481917

Change-Id: Ie070b28a78503eeb3003493b5f130a4dcd9b1275
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1996137
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/pmu/clk/clk.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -990,6 +990,7 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
 	int status = 0;
 	u8 i = 0, gpcclk_domain=0;
 	u32 gpcclk_clkmhz=0, gpcclk_voltuv=0;
+	u32 vmin_uv = 0;
 
 	(void) memset(&change_input, 0,
 		sizeof(struct ctrl_perf_change_seq_change_input));
@@ -1029,6 +1030,16 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
 	status = clk_domain_freq_to_volt(g, gpcclk_domain,
 		&gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
 
+	status = g->ops.pmu_ver.volt.volt_get_vmin(g, &vmin_uv);
+	if(status != 0)
+	{
+		nvgpu_pmu_dbg(g, "Get vmin failed, proceeding with freq_to_volt value");
+	}
+	if((status == 0) && (vmin_uv > gpcclk_voltuv)) {
+		gpcclk_voltuv = vmin_uv;
+		nvgpu_pmu_dbg(g, "Vmin is higher than evaluated Volt");
+	}
+
 	change_input.volt[0].voltage_uv = gpcclk_voltuv;
 	change_input.volt[0].voltage_min_noise_unaware_uv = gpcclk_voltuv;
 	change_input.volt_rails_mask.super.data[0] = 1U;

drivers/gpu/nvgpu/common/pmu/pmu_fw.c

@@ -1327,6 +1327,8 @@ int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
 					nvgpu_clk_set_boot_fll_clk_gv10x;
 			} else {
 				g->ops.pmu_ver.clk.clk_set_boot_clk = NULL;
+				g->ops.pmu_ver.volt.volt_get_vmin =
+					nvgpu_volt_get_vmin_tu10x;
 			}
 		} else {
 			g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =

drivers/gpu/nvgpu/common/pmu/volt/volt_pmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -387,3 +387,29 @@ int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
 
 }
 
+int nvgpu_volt_get_vmin_tu10x(struct gk20a *g, u32 *vmin_uv)
+{
+	struct boardobjgrp *pboardobjgrp;
+	struct boardobj *pboardobj = NULL;
+	struct voltage_rail *volt_rail = NULL;
+	int status;
+	u8 index;
+
+	status = nvgpu_volt_rail_boardobj_grp_get_status(g);
+	if (status != 0) {
+		nvgpu_err(g, "Vfe_var get status failed");
+		return status;
+	}
+
+	pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
+
+	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
+		volt_rail = (struct voltage_rail *)(void *)pboardobj;
+		if (volt_rail->vmin_limitu_v != 0U) {
+			*vmin_uv = volt_rail->vmin_limitu_v;
+			return status;
+		}
+	}
+	return status;
+}
+

drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -415,6 +415,68 @@ static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
 	return 0;
 }
 
+static int volt_rail_obj_update(struct gk20a *g,
+		struct boardobj *board_obj_ptr,
+		struct nv_pmu_boardobj *ppmudata)
+{
+	struct voltage_rail *volt_rail_obj;
+	struct nv_pmu_volt_volt_rail_boardobj_get_status *pstatus;
+
+	nvgpu_log_info(g, " ");
+
+	volt_rail_obj = (struct voltage_rail *)(void *)board_obj_ptr;
+	pstatus = (struct nv_pmu_volt_volt_rail_boardobj_get_status *)
+		(void *)ppmudata;
+
+	if (pstatus->super.type != volt_rail_obj->super.type) {
+		nvgpu_err(g, "pmu data and boardobj type not matching");
+		return -EINVAL;
+	}
+
+	/* Updating only vmin as per requirement, later other fields can be added */
+	volt_rail_obj->vmin_limitu_v = pstatus->vmin_limitu_v;
+	return 0;
+}
+
+int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g)
+{
+	struct boardobjgrp *pboardobjgrp;
+	struct boardobjgrpmask *pboardobjgrpmask;
+	struct nv_pmu_boardobjgrp_super *pboardobjgrppmu;
+	struct boardobj *pboardobj = NULL;
+	struct nv_pmu_boardobj_query *pboardobjpmustatus = NULL;
+	int status;
+	u8 index;
+
+	nvgpu_log_info(g, " ");
+
+	pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
+	pboardobjgrpmask = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.mask.super;
+	status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
+	if (status != 0) {
+		nvgpu_err(g, "err getting boardobjs from pmu");
+		return status;
+	}
+	pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf;
+
+	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
+		status = pboardobjgrp->pmustatusinstget(g,
+				(struct nv_pmu_boardobjgrp *)(void *)pboardobjgrppmu,
+				&pboardobjpmustatus, index);
+		if (status != 0) {
+			nvgpu_err(g, "could not get status object instance");
+			return status;
+		}
+		status = volt_rail_obj_update(g, pboardobj,
+				(struct nv_pmu_boardobj *)(void *)pboardobjpmustatus);
+		if (status != 0) {
+			nvgpu_err(g, "could not update volt rail status");
+			return status;
+		}
+	}
+	return 0;
+}
+
 int volt_rail_sw_setup(struct gk20a *g)
 {
 	int status = 0;

drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h

@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -63,6 +63,7 @@ struct voltage_rail {
 	u32 ov_limit_vfe_equ_mon_handle;
 	struct boardobjgrpmask_e32 volt_dev_mask;
 	s32  volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
+	u32 vmin_limitu_v;
 };
 
 u8 volt_rail_vbios_volt_domain_convert_to_internal

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1009,6 +1009,7 @@ struct gpu_ops {
 			int (*volt_get_voltage)(struct gk20a *g,
 				u8 volt_domain, u32 *pvoltage_uv);
 			int (*volt_send_load_cmd_to_pmu)(struct gk20a *g);
+			int (*volt_get_vmin)(struct gk20a *g, u32 *vmin_uv);
 		} volt;
 		struct {
 			u32 (*get_vbios_clk_domain)(u32 vbios_domain);

drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h

@@ -80,5 +80,7 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
 
 int volt_policy_sw_setup(struct gk20a *g);
 int volt_policy_pmu_setup(struct gk20a *g);
+int nvgpu_volt_rail_boardobj_grp_get_status(struct gk20a *g);
+int nvgpu_volt_get_vmin_tu10x(struct gk20a *g, u32 *vmin_uv);
 
 #endif /* NVGPU_PMU_VOLT_H */