gpu: nvgpu: gm20b: MISRA 21.2 header guard fixes

MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gm20b hw headers by renaming them to follow the convention, 'NVGPU_HEADER_NAME'. JIRA NVGPU-1028 Change-Id: I49e4af38b83d54a5814ab3e9246a8af1f1e55fe8 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829976 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2025-12-24 10:34:43 +03:00 · 2018-09-28 12:32:45 +05:30
parent 56512f1f95
commit f0506d28d6
26 changed files with 68 additions and 68 deletions
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_bus_gm20b_h_
-#define _hw_bus_gm20b_h_
+#ifndef NVGPU_HW_BUS_GM20B_H
+#define NVGPU_HW_BUS_GM20B_H

 static inline u32 bus_bar0_window_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_ccsr_gm20b_h_
-#define _hw_ccsr_gm20b_h_
+#ifndef NVGPU_HW_CCSR_GM20B_H
+#define NVGPU_HW_CCSR_GM20B_H

 static inline u32 ccsr_channel_inst_r(u32 i)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_ce2_gm20b_h_
-#define _hw_ce2_gm20b_h_
+#ifndef NVGPU_HW_CE2_GM20B_H
+#define NVGPU_HW_CE2_GM20B_H

 static inline u32 ce2_intr_status_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_ctxsw_prog_gm20b_h_
-#define _hw_ctxsw_prog_gm20b_h_
+#ifndef NVGPU_HW_CTXSW_PROG_GM20B_H
+#define NVGPU_HW_CTXSW_PROG_GM20B_H

 static inline u32 ctxsw_prog_fecs_header_v(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_falcon_gm20b_h_
-#define _hw_falcon_gm20b_h_
+#ifndef NVGPU_HW_FALCON_GM20B_H
+#define NVGPU_HW_FALCON_GM20B_H

 static inline u32 falcon_falcon_irqsset_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_fb_gm20b_h_
-#define _hw_fb_gm20b_h_
+#ifndef NVGPU_HW_FB_GM20B_H
+#define NVGPU_HW_FB_GM20B_H

 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_fifo_gm20b_h_
-#define _hw_fifo_gm20b_h_
+#ifndef NVGPU_HW_FIFO_GM20B_H
+#define NVGPU_HW_FIFO_GM20B_H

 static inline u32 fifo_bar1_base_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_flush_gm20b_h_
-#define _hw_flush_gm20b_h_
+#ifndef NVGPU_HW_FLUSH_GM20B_H
+#define NVGPU_HW_FLUSH_GM20B_H

 static inline u32 flush_l2_system_invalidate_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_fuse_gm20b_h_
-#define _hw_fuse_gm20b_h_
+#ifndef NVGPU_HW_FUSE_GM20B_H
+#define NVGPU_HW_FUSE_GM20B_H

 static inline u32 fuse_status_opt_gpc_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_gmmu_gm20b_h_
-#define _hw_gmmu_gm20b_h_
+#ifndef NVGPU_HW_GMMU_GM20B_H
+#define NVGPU_HW_GMMU_GM20B_H

 static inline u32 gmmu_pde_aperture_big_w(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_gr_gm20b_h_
-#define _hw_gr_gm20b_h_
+#ifndef NVGPU_HW_GR_GM20B_H
+#define NVGPU_HW_GR_GM20B_H

 static inline u32 gr_intr_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_ltc_gm20b_h_
-#define _hw_ltc_gm20b_h_
+#ifndef NVGPU_HW_LTC_GM20B_H
+#define NVGPU_HW_LTC_GM20B_H

 static inline u32 ltc_pltcg_base_v(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_mc_gm20b_h_
-#define _hw_mc_gm20b_h_
+#ifndef NVGPU_HW_MC_GM20B_H
+#define NVGPU_HW_MC_GM20B_H

 static inline u32 mc_boot_0_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pbdma_gm20b_h_
-#define _hw_pbdma_gm20b_h_
+#ifndef NVGPU_HW_PBDMA_GM20B_H
+#define NVGPU_HW_PBDMA_GM20B_H

 static inline u32 pbdma_gp_entry1_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_perf_gm20b_h_
-#define _hw_perf_gm20b_h_
+#ifndef NVGPU_HW_PERF_GM20B_H
+#define NVGPU_HW_PERF_GM20B_H

 static inline u32 perf_pmmsys_base_v(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pram_gm20b_h_
-#define _hw_pram_gm20b_h_
+#ifndef NVGPU_HW_PRAM_GM20B_H
+#define NVGPU_HW_PRAM_GM20B_H

 static inline u32 pram_data032_r(u32 i)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pri_ringmaster_gm20b_h_
-#define _hw_pri_ringmaster_gm20b_h_
+#ifndef NVGPU_HW_PRI_RINGMASTER_GM20B_H
+#define NVGPU_HW_PRI_RINGMASTER_GM20B_H

 static inline u32 pri_ringmaster_command_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pri_ringstation_gpc_gm20b_h_
-#define _hw_pri_ringstation_gpc_gm20b_h_
+#ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GM20B_H
+#define NVGPU_HW_PRI_RINGSTATION_GPC_GM20B_H

 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pri_ringstation_sys_gm20b_h_
-#define _hw_pri_ringstation_sys_gm20b_h_
+#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GM20B_H
+#define NVGPU_HW_PRI_RINGSTATION_SYS_GM20B_H

 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_proj_gm20b_h_
-#define _hw_proj_gm20b_h_
+#ifndef NVGPU_HW_PROJ_GM20B_H
+#define NVGPU_HW_PROJ_GM20B_H

 static inline u32 proj_gpc_base_v(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_pwr_gm20b_h_
-#define _hw_pwr_gm20b_h_
+#ifndef NVGPU_HW_PWR_GM20B_H
+#define NVGPU_HW_PWR_GM20B_H

 static inline u32 pwr_falcon_irqsset_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_ram_gm20b_h_
-#define _hw_ram_gm20b_h_
+#ifndef NVGPU_HW_RAM_GM20B_H
+#define NVGPU_HW_RAM_GM20B_H

 static inline u32 ram_in_ramfc_s(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_therm_gm20b_h_
-#define _hw_therm_gm20b_h_
+#ifndef NVGPU_HW_THERM_GM20B_H
+#define NVGPU_HW_THERM_GM20B_H

 static inline u32 therm_use_a_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_timer_gm20b_h_
-#define _hw_timer_gm20b_h_
+#ifndef NVGPU_HW_TIMER_GM20B_H
+#define NVGPU_HW_TIMER_GM20B_H

 static inline u32 timer_pri_timeout_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_top_gm20b_h_
-#define _hw_top_gm20b_h_
+#ifndef NVGPU_HW_TOP_GM20B_H
+#define NVGPU_HW_TOP_GM20B_H

 static inline u32 top_num_gpcs_r(void)
 {
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
 *         comparison with unshifted values appropriate for use in field <y>
 *         of register <x>.
 */
-#ifndef _hw_trim_gm20b_h_
-#define _hw_trim_gm20b_h_
+#ifndef NVGPU_HW_TRIM_GM20B_H
+#define NVGPU_HW_TRIM_GM20B_H

 static inline u32 trim_sys_gpcpll_cfg_r(void)
 {