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gpu: nvgpu: add speculative barrier

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Data can be speculativerly stored and
code flow can be hijacked.

To mitigate this problem insert a
speculation barrier.

Bug 200447167

Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08
Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972221
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Ranjanikar Nikhil Prabhakarrao
2018-12-13 17:29:20 +05:30
committed by mobile promotions
parent 001dbdb2fc
commit f0762ed483
13 changed files with 43 additions and 0 deletions
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11
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -367,6 +367,7 @@ gk20a_ctrl_ioctl_gpu_characteristics(
if (request->gpu_characteristics_buf_size > 0) {
size_t write_size = sizeof(gpu);
nvgpu_speculation_barrier();
if (write_size > request->gpu_characteristics_buf_size)
write_size = request->gpu_characteristics_buf_size;
@@ -557,6 +558,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
if (args->mask_buf_size > 0) {
size_t write_size = gpc_tpc_mask_size;
nvgpu_speculation_barrier();
if (write_size > args->mask_buf_size)
write_size = args->mask_buf_size;
@@ -581,6 +583,7 @@ static int gk20a_ctrl_get_fbp_l2_masks(
if (args->mask_buf_size > 0) {
size_t write_size = fbp_l2_mask_size;
nvgpu_speculation_barrier();
if (write_size > args->mask_buf_size)
write_size = args->mask_buf_size;
@@ -1219,6 +1222,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
nvgpu_gpu_convert_clk_domain(clk_info.clk_domain)))
return -EINVAL;
}
nvgpu_speculation_barrier();
entry = (struct nvgpu_gpu_clk_info __user *)
(uintptr_t)args->clk_info_entries;
@@ -1238,6 +1242,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), freq_mhz);
}
nvgpu_speculation_barrier();
ret = nvgpu_clk_arb_commit_request_fd(g, session, fd);
if (ret < 0)
return ret;
@@ -1307,6 +1312,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g,
clk_info.clk_type = args->clk_type;
}
nvgpu_speculation_barrier();
switch (clk_info.clk_type) {
case NVGPU_GPU_CLK_TYPE_TARGET:
err = nvgpu_clk_arb_get_session_target_mhz(session,
@@ -1340,6 +1346,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g,
return -EFAULT;
}
nvgpu_speculation_barrier();
args->num_entries = num_entries;
return 0;
@@ -1380,6 +1387,7 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g,
if (err)
return err;
nvgpu_speculation_barrier();
switch (args->which) {
case NVGPU_GPU_VOLTAGE_CORE:
err = volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &args->voltage);
@@ -1602,6 +1610,7 @@ static int nvgpu_gpu_set_deterministic_opts(struct gk20a *g,
break;
}
nvgpu_speculation_barrier();
nvgpu_rwsem_up_read(&g->deterministic_busy);
out:
@@ -1646,6 +1655,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
gk20a_idle(g);
}
nvgpu_speculation_barrier();
switch (cmd) {
case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE:
get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf;
@@ -1692,6 +1702,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
zbc_val->format = set_table_args->format;
zbc_val->type = set_table_args->type;
nvgpu_speculation_barrier();
switch (zbc_val->type) {
case GK20A_ZBC_TYPE_COLOR:
for (i = 0U; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {