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gpu: nvgpu: add speculative barrier

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Data can be speculativerly stored and
code flow can be hijacked.

To mitigate this problem insert a
speculation barrier.

Bug 200447167

Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08
Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972221
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Ranjanikar Nikhil Prabhakarrao
2018-12-13 17:29:20 +05:30
committed by mobile promotions
parent 001dbdb2fc
commit f0762ed483
13 changed files with 43 additions and 0 deletions
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10
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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@@ -306,6 +306,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
if (args->sm_error_state_record_size > 0) {
size_t write_size = sizeof(*sm_error_state);
nvgpu_speculation_barrier();
if (write_size > args->sm_error_state_record_size)
write_size = args->sm_error_state_record_size;
@@ -353,6 +354,7 @@ static int nvgpu_dbg_timeout_enable(struct dbg_session_gk20a *dbg_s,
nvgpu_log(g, gpu_dbg_gpu_dbg, "Timeouts mode requested : %d",
timeout_mode);
nvgpu_speculation_barrier();
switch (timeout_mode) {
case NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE:
if (dbg_s->is_timeout_disabled == true)
@@ -909,6 +911,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
ops_offset += num_ops;
}
nvgpu_speculation_barrier();
nvgpu_kfree(g, linux_fragment);
/* enable powergate, if previously disabled */
@@ -999,6 +1002,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode)
{
nvgpu_speculation_barrier();
switch (mode){
case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW:
return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW;
@@ -1098,6 +1102,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
goto clean_up;
}
nvgpu_speculation_barrier();
switch (action) {
case NVGPU_DBG_GPU_SUSPEND_ALL_SMS:
gr_gk20a_suspend_context(ch);
@@ -1311,6 +1316,7 @@ static int gk20a_dbg_gpu_events_ctrl(struct dbg_session_gk20a *dbg_s,
return -EINVAL;
}
nvgpu_speculation_barrier();
switch (args->cmd) {
case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE:
gk20a_dbg_gpu_events_enable(dbg_s);
@@ -1480,6 +1486,7 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s,
if (err)
return err;
nvgpu_speculation_barrier();
switch (args->action) {
case NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS:
err = g->ops.gr.suspend_contexts(g, dbg_s,
@@ -1571,6 +1578,7 @@ static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s,
size -= access_size;
offset += access_size;
}
nvgpu_speculation_barrier();
fail_idle:
gk20a_idle(g);
@@ -1811,6 +1819,7 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *db
u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE;
struct channel_gk20a *ch = NULL;
nvgpu_speculation_barrier();
switch (args->exception_type_mask) {
case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL:
sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL;
@@ -1889,6 +1898,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
/* protect from threaded user space calls */
nvgpu_mutex_acquire(&dbg_s->ioctl_lock);
nvgpu_speculation_barrier();
switch (cmd) {
case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL:
err = dbg_bind_channel_gk20a(dbg_s,