From f0896f94e19d364dbfac997125b3badf8064488f Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 21 Apr 2020 10:26:29 +0530 Subject: [PATCH] gpu: nvgpu: Add falcon gops Add falcon gops for accessing below constants. This is required for nvgpu-next. falcon_falcon_dmemc_blk_m falcon_falcon_imemc_blk_f JIRA NVGPU-4834 Change-Id: I1a60f473470a7a03fb31dceecfccd91fcc690de9 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322736 Reviewed-by: Seema Khowala Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c | 6 +++--- drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h | 4 +++- drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c | 16 ++++++++++++++-- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 ++ drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h | 4 +++- 8 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c index 39858a060..10fbdd54a 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -64,7 +64,7 @@ int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn, bytes = size & 0x3U; addr_mask = falcon_falcon_dmemc_offs_m() | - falcon_falcon_dmemc_blk_m(); + g->ops.falcon.dmemc_blk_mask(); src &= addr_mask; @@ -107,7 +107,7 @@ int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, nvgpu_writel(g, base_addr + falcon_falcon_imemc_r(port), falcon_falcon_imemc_offs_f(src >> 2) | - falcon_falcon_imemc_blk_f(blk) | + g->ops.falcon.imemc_blk_field(blk) | falcon_falcon_dmemc_aincr_f(1)); for (i = 0; i < words; i++) { diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h index c2fa5dd6a..163903de3 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -61,6 +61,8 @@ #define FALCON_DMEM_BLKSIZE2 8U +u32 gk20a_falcon_dmemc_blk_mask(void); +u32 gk20a_falcon_imemc_blk_field(u32 blk); void gk20a_falcon_reset(struct nvgpu_falcon *flcn); bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn); bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn); diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c index 4b826b008..f23896609 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c @@ -29,6 +29,16 @@ #include +u32 gk20a_falcon_dmemc_blk_mask(void) +{ + return falcon_falcon_dmemc_blk_m(); +} + +u32 gk20a_falcon_imemc_blk_field(u32 blk) +{ + return falcon_falcon_imemc_blk_f(blk); +} + static inline u32 gk20a_falcon_readl(struct nvgpu_falcon *flcn, u32 offset) { return nvgpu_readl(flcn->g, @@ -170,6 +180,7 @@ static void falcon_copy_to_dmem_unaligned_src(struct nvgpu_falcon *flcn, int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port) { + struct gk20a *g = flcn->g; u32 i = 0U, words = 0U, bytes = 0U; u32 data = 0U, addr_mask = 0U; u32 *src_u32 = NULL; @@ -180,7 +191,7 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, bytes = size & 0x3U; addr_mask = falcon_falcon_dmemc_offs_m() | - falcon_falcon_dmemc_blk_m(); + g->ops.falcon.dmemc_blk_mask(); dst &= addr_mask; @@ -280,6 +291,7 @@ static void falcon_copy_to_imem_unaligned_src(struct nvgpu_falcon *flcn, int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag) { + struct gk20a *g = flcn->g; u32 *src_u32 = NULL; u32 words = 0U; u32 blk = 0U; @@ -295,7 +307,7 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, gk20a_falcon_writel(flcn, falcon_falcon_imemc_r(port), falcon_falcon_imemc_offs_f(dst >> 2) | - falcon_falcon_imemc_blk_f(blk) | + g->ops.falcon.imemc_blk_field(blk) | /* Set Auto-Increment on write */ falcon_falcon_imemc_aincw_f(1) | falcon_falcon_imemc_secure_f(sec ? 1U : 0U)); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 86740e508..5103e5e80 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -1062,6 +1062,8 @@ static const struct gpu_ops gm20b_ops = { .get_ports_count = gk20a_falcon_get_ports_count, .copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_imem = gk20a_falcon_copy_to_imem, + .dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask, + .imemc_blk_field = gk20a_falcon_imemc_blk_field, .bootstrap = gk20a_falcon_bootstrap, .mailbox_read = gk20a_falcon_mailbox_read, .mailbox_write = gk20a_falcon_mailbox_write, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 3b9af458e..e284391f2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -1168,6 +1168,8 @@ static const struct gpu_ops gp10b_ops = { .get_ports_count = gk20a_falcon_get_ports_count, .copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_imem = gk20a_falcon_copy_to_imem, + .dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask, + .imemc_blk_field = gk20a_falcon_imemc_blk_field, .bootstrap = gk20a_falcon_bootstrap, .mailbox_read = gk20a_falcon_mailbox_read, .mailbox_write = gk20a_falcon_mailbox_write, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 43db65d8b..5ddfde04e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1423,6 +1423,8 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7)) .get_ports_count = gk20a_falcon_get_ports_count, .copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_imem = gk20a_falcon_copy_to_imem, + .dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask, + .imemc_blk_field = gk20a_falcon_imemc_blk_field, .bootstrap = gk20a_falcon_bootstrap, .mailbox_read = gk20a_falcon_mailbox_read, .mailbox_write = gk20a_falcon_mailbox_write, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index a5bad9621..2b66defd3 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1468,6 +1468,8 @@ static const struct gpu_ops tu104_ops = { .get_ports_count = gk20a_falcon_get_ports_count, .copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_imem = gk20a_falcon_copy_to_imem, + .dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask, + .imemc_blk_field = gk20a_falcon_imemc_blk_field, .bootstrap = gk20a_falcon_bootstrap, .mailbox_read = gk20a_falcon_mailbox_read, .mailbox_write = gk20a_falcon_mailbox_write, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h index b3263ac58..55cc7df32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -50,6 +50,8 @@ struct gops_falcon { int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag); + u32 (*dmemc_blk_mask)(void); + u32 (*imemc_blk_field)(u32 blk); void (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector); u32 (*mailbox_read)(struct nvgpu_falcon *flcn,