nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: vgpu: initialize tgid for FECS trace

Browse Source 
- "tsg->tgid" is used for getting "pid" of contexts
in FECS trace support.
- "tsg->tgid" was unitialized for virtualized platforms
which was resulting in "pid" to be "0" for all contexts.
- This patch initializes tgid to fix this issue.

Jira NVGPU-1880

Change-Id: I59c30aca4609d61d09c465b7ec39983095af669b
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaibhav Kachore
2019-03-26 16:09:22 +05:30
committed by mobile promotions
parent 22cb47c077
commit f0a5f97ebb
4 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -558,7 +558,7 @@ static struct tsg_gk20a *gk20a_tsg_acquire_unused_tsg(struct fifo_gk20a *f)
return tsg; return tsg;
} }
int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg) int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg, pid_t pid)
{ {
u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr.config); u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(g->gr.config);
int err; int err;
@@ -576,6 +576,7 @@ int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg)
return err; return err;
} }
tsg->tgid = pid;
tsg->g = g; tsg->g = g;
tsg->num_active_channels = 0U; tsg->num_active_channels = 0U;
nvgpu_ref_init(&tsg->refcount); nvgpu_ref_init(&tsg->refcount);
@@ -625,15 +626,13 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid)
return NULL; return NULL;
} }
err = gk20a_tsg_open_common(g, tsg); err = gk20a_tsg_open_common(g, tsg, pid);
if (err != 0) { if (err != 0) {
release_used_tsg(&g->fifo, tsg); release_used_tsg(&g->fifo, tsg);
nvgpu_err(g, "tsg %d open failed %d", tsg->tsgid, err); nvgpu_err(g, "tsg %d open failed %d", tsg->tsgid, err);
return NULL; return NULL;
} }
tsg->tgid = pid;
nvgpu_log(g, gpu_dbg_fn, "tsg opened %d\n", tsg->tsgid); nvgpu_log(g, gpu_dbg_fn, "tsg opened %d\n", tsg->tsgid);
return tsg; return tsg;

1
drivers/gpu/nvgpu/common/vgpu/tsg_vgpu.c
View File

@@ -43,6 +43,7 @@ int vgpu_tsg_open(struct tsg_gk20a *tsg)
msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN; msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
msg.handle = vgpu_get_handle(tsg->g); msg.handle = vgpu_get_handle(tsg->g);
p->tsg_id = tsg->tsgid; p->tsg_id = tsg->tsgid;
p->pid = tsg->tgid;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret; err = err ? err : msg.ret;
if (err) { if (err) {

2
drivers/gpu/nvgpu/include/nvgpu/tsg.h
View File

@@ -81,7 +81,7 @@ struct tsg_gk20a {
struct nvgpu_mutex sm_exception_mask_lock; struct nvgpu_mutex sm_exception_mask_lock;
}; };
int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg); int gk20a_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg, pid_t pid);
struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid); struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid);
void gk20a_tsg_release_common(struct gk20a *g, struct tsg_gk20a *tsg); void gk20a_tsg_release_common(struct gk20a *g, struct tsg_gk20a *tsg);
void gk20a_tsg_release(struct nvgpu_ref *ref); void gk20a_tsg_release(struct nvgpu_ref *ref);

1
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -418,6 +418,7 @@ struct tegra_vgpu_tsg_timeslice_params {
struct tegra_vgpu_tsg_open_rel_params { struct tegra_vgpu_tsg_open_rel_params {
u32 tsg_id; u32 tsg_id;
pid_t pid;
}; };
/* level follows nvgpu.h definitions */ /* level follows nvgpu.h definitions */