From f0de6fa54a1147f6ac24d7ff9224aa3b6c1373af Mon Sep 17 00:00:00 2001 From: mkumbar Date: Thu, 28 May 2020 13:48:34 +0530 Subject: [PATCH] gpu: nvgpu: sec2: update sec2 interfaces update sec2 rtos interfaces to support next dgpu sec2 ucode. JIRA NVGPU-5468 Change-Id: I534a6eded8a9525dc09e5f57e46bef36f1a4e81b Signed-off-by: mkumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352103 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h | 11 ++++++++++- drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h | 5 ++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h index 18d3112b9..0c292026e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -48,6 +48,12 @@ struct nv_sec2_acr_cmd_bootstrap_falcon { /* ID to identify Falcon, ref FALCON_ID_ */ u32 falcon_id; + + /* Falcon Instance bootstrapped by ACR */ + u32 falcon_instance; + + /* Mask of indexes of same falcon to be multi bootstrapped by ACR */ + u32 falcon_Index_Mask; }; #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U @@ -83,6 +89,9 @@ struct nv_sec2_acr_msg_bootstrap_falcon { /* Bootstrapped falcon ID by ACR */ u32 falcon_id; + + /* Falcon Instance bootstrapped by ACR */ + u32 falcon_instance; }; /* diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h index 979e63983..072617bb5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -58,6 +58,9 @@ struct sec2_init_msg_sec2_init { u32 nv_managed_area_offset; u16 nv_managed_area_size; + /* Unused, kept for the binary compatibility */ + u8 rsvd_1[16]; + u8 rsvd_2[16]; }; union nv_flcn_msg_sec2_init {