From f11cd6d4f3a5140e3f5f806ead3cf812295b7832 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 1 Aug 2019 13:29:05 -0700 Subject: [PATCH] gpu: nvgpu: fix register name related to mme_shadow_ram New register generators generated correct kernel headers for mme_shadow_ram register and associated fields. Modified code to use this updated hw defs. JIRA NVGPU-3558 Change-Id: I2d1f4a4bd713abc16414208b2a4efccd114a6a59 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2167093 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Raghuram Kothakota Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c | 12 ++++++------ .../gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 6 +++--- .../gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 6 +++--- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 6 +++--- .../gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h | 6 +++--- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c index 9136f47a6..136133f68 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c @@ -377,22 +377,22 @@ void gm20b_gr_init_load_method_init(struct gk20a *g, u32 last_method_data = 0U; if (sw_method_init->count != 0U) { - nvgpu_writel(g, gr_pri_mme_shadow_raw_data_r(), + nvgpu_writel(g, gr_pri_mme_shadow_ram_data_r(), sw_method_init->l[0U].value); - nvgpu_writel(g, gr_pri_mme_shadow_raw_index_r(), - gr_pri_mme_shadow_raw_index_write_trigger_f() | + nvgpu_writel(g, gr_pri_mme_shadow_ram_index_r(), + gr_pri_mme_shadow_ram_index_write_trigger_f() | sw_method_init->l[0U].addr); last_method_data = sw_method_init->l[0U].value; } for (i = 1U; i < sw_method_init->count; i++) { if (sw_method_init->l[i].value != last_method_data) { - nvgpu_writel(g, gr_pri_mme_shadow_raw_data_r(), + nvgpu_writel(g, gr_pri_mme_shadow_ram_data_r(), sw_method_init->l[i].value); last_method_data = sw_method_init->l[i].value; } - nvgpu_writel(g, gr_pri_mme_shadow_raw_index_r(), - gr_pri_mme_shadow_raw_index_write_trigger_f() | + nvgpu_writel(g, gr_pri_mme_shadow_ram_index_r(), + gr_pri_mme_shadow_ram_index_write_trigger_f() | sw_method_init->l[i].addr); } } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index dce06b208..817c8137a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -204,9 +204,9 @@ (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) #define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) #define gr_fe_tpc_fs_r() (0x004041c4U) -#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) -#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) -#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_pri_mme_shadow_ram_index_r() (0x00404488U) +#define gr_pri_mme_shadow_ram_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_ram_data_r() (0x0040448cU) #define gr_mme_hww_esr_r() (0x00404490U) #define gr_mme_hww_esr_reset_active_f() (0x40000000U) #define gr_mme_hww_esr_en_enable_f() (0x80000000U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index 840c598de..424883beb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h @@ -269,9 +269,9 @@ (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) #define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) #define gr_fe_tpc_fs_r() (0x004041c4U) -#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) -#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) -#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_pri_mme_shadow_ram_index_r() (0x00404488U) +#define gr_pri_mme_shadow_ram_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_ram_data_r() (0x0040448cU) #define gr_mme_hww_esr_r() (0x00404490U) #define gr_mme_hww_esr_reset_active_f() (0x40000000U) #define gr_mme_hww_esr_en_enable_f() (0x80000000U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 6b14c4734..04d6e8d41 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -588,9 +588,9 @@ #define gr_fe_tpc_pesmask_req_m() (U32(0x1U) << 31U) #define gr_fe_tpc_pesmask_req_send_f() (0x80000000U) #define gr_fe_tpc_pesmask_mask_m() (U32(0xffffU) << 0U) -#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) -#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) -#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_pri_mme_shadow_ram_index_r() (0x00404488U) +#define gr_pri_mme_shadow_ram_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_ram_data_r() (0x0040448cU) #define gr_mme_hww_esr_r() (0x00404490U) #define gr_mme_hww_esr_reset_active_f() (0x40000000U) #define gr_mme_hww_esr_en_enable_f() (0x80000000U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h index 65a9a691d..e0430221d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h @@ -360,9 +360,9 @@ #define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) #define gr_fe_tpc_fs_r(i)\ (nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U))) -#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) -#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) -#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_pri_mme_shadow_ram_index_r() (0x00404488U) +#define gr_pri_mme_shadow_ram_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_ram_data_r() (0x0040448cU) #define gr_mme_hww_esr_r() (0x00404490U) #define gr_mme_hww_esr_missing_macro_data_pending_f() (0x1U) #define gr_mme_hww_esr_illegal_opcode_pending_f() (0x4U)