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gpu: nvgpu: add get_cbm_alpha_cb_size hal

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Add get_cbm_alpha_cb_size hal to avoid duplication of code to new chips.

Bug 4134898

Change-Id: I59fe7065b142b3296bfa3b20cb3198ac1ec859ce
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2911335
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2023-05-26 17:46:27 +00:00
committed by mobile promotions
parent 78bef566dd
commit f1613a300b
7 changed files with 31 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
View File

@@ -1,7 +1,7 @@
/* /*
* GV11b GPU GR * GV11b GPU GR
* *
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -64,6 +64,11 @@
#define PRI_BROADCAST_FLAGS_SMPC BIT32(17) #define PRI_BROADCAST_FLAGS_SMPC BIT32(17)
u32 gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size(void)
{
return gr_gpc0_ppc0_cbm_alpha_cb_size_r();
}
void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
{ {
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g); struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
@@ -81,7 +86,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
alpha_cb_size = alpha_cb_size_max; alpha_cb_size = alpha_cb_size_max;
} }
gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), nvgpu_writel(g, gr_ds_tga_constraintlogic_alpha_r(),
(gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) &
~gr_ds_tga_constraintlogic_alpha_cbsize_f(~U32(0U))) | ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~U32(0U))) |
gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size)); gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size));
@@ -90,7 +95,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() / gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() /
gr_pd_ab_dist_cfg1_max_output_granularity_v(); gr_pd_ab_dist_cfg1_max_output_granularity_v();
gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), nvgpu_writel(g, gr_pd_ab_dist_cfg1_r(),
gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
gr_pd_ab_dist_cfg1_max_batches_init_f()); gr_pd_ab_dist_cfg1_max_batches_init_f());
@@ -103,15 +108,26 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
ppc_index < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index); ppc_index < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index);
ppc_index++) { ppc_index++) {
val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + val = nvgpu_readl(g, nvgpu_safe_add_u32(
stride + ppc_in_gpc_stride * ppc_index); nvgpu_safe_add_u32(
g->ops.gr.get_cbm_alpha_cb_size(),
stride),
nvgpu_safe_mult_u32(
ppc_in_gpc_stride,
ppc_index)));
val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(), val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(),
gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size * gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size *
nvgpu_gr_config_get_pes_tpc_count(gr->config, gpc_index, ppc_index))); nvgpu_gr_config_get_pes_tpc_count(gr->config,
gpc_index, ppc_index)));
gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + nvgpu_writel(g, nvgpu_safe_add_u32(
stride + ppc_in_gpc_stride * ppc_index, val); nvgpu_safe_add_u32(
g->ops.gr.get_cbm_alpha_cb_size(),
stride),
nvgpu_safe_mult_u32(
ppc_in_gpc_stride,
ppc_index)), val);
} }
} }
} }

3
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
View File

@@ -1,7 +1,7 @@
/* /*
* GV11B GPU GR * GV11B GPU GR
* *
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -31,6 +31,7 @@ struct gk20a;
struct nvgpu_warpstate; struct nvgpu_warpstate;
struct nvgpu_debug_context; struct nvgpu_debug_context;
u32 gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size(void);
void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
int gr_gv11b_dump_gr_status_regs(struct gk20a *g, int gr_gv11b_dump_gr_status_regs(struct gk20a *g,

1
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -821,6 +821,7 @@ static const struct gops_gr ga100_ops_gr = {
.gr_suspend = nvgpu_gr_suspend, .gr_suspend = nvgpu_gr_suspend,
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
.get_gr_status = gr_gm20b_get_gr_status, .get_gr_status = gr_gm20b_get_gr_status,
.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_ga100_set_circular_buffer_size, .set_circular_buffer_size = gr_ga100_set_circular_buffer_size,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,

1
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -829,6 +829,7 @@ static const struct gops_gr ga10b_ops_gr = {
#endif #endif
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
.get_gr_status = gr_gm20b_get_gr_status, .get_gr_status = gr_gm20b_get_gr_status,
.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
.set_circular_buffer_size = gr_ga10b_set_circular_buffer_size, .set_circular_buffer_size = gr_ga10b_set_circular_buffer_size,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -683,6 +683,7 @@ static const struct gops_gr gv11b_ops_gr = {
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
.get_gr_status = gr_gm20b_get_gr_status, .get_gr_status = gr_gm20b_get_gr_status,
.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -720,6 +720,7 @@ static const struct gops_gr tu104_ops_gr = {
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
.get_gr_status = gr_gm20b_get_gr_status, .get_gr_status = gr_gm20b_get_gr_status,
.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size, .set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs, .get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,

1
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
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@@ -1245,6 +1245,7 @@ struct gops_gr {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
u32 (*get_gr_status)(struct gk20a *g); u32 (*get_gr_status)(struct gk20a *g);
u32 (*get_cbm_alpha_cb_size)(void);
void (*set_alpha_circular_buffer_size)(struct gk20a *g, void (*set_alpha_circular_buffer_size)(struct gk20a *g,
u32 data); u32 data);
void (*set_circular_buffer_size)(struct gk20a *g, u32 data); void (*set_circular_buffer_size)(struct gk20a *g, u32 data);