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gpu: nvgpu: add get_cbm_alpha_cb_size hal
Add get_cbm_alpha_cb_size hal to avoid duplication of code to new chips. Bug 4134898 Change-Id: I59fe7065b142b3296bfa3b20cb3198ac1ec859ce Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2911335 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-by: Martin Radev <mradev@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* GV11b GPU GR
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*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -64,6 +64,11 @@
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#define PRI_BROADCAST_FLAGS_SMPC BIT32(17)
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u32 gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size(void)
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{
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return gr_gpc0_ppc0_cbm_alpha_cb_size_r();
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}
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void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
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{
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struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
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@@ -81,7 +86,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
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alpha_cb_size = alpha_cb_size_max;
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}
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gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(),
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nvgpu_writel(g, gr_ds_tga_constraintlogic_alpha_r(),
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(gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) &
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~gr_ds_tga_constraintlogic_alpha_cbsize_f(~U32(0U))) |
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gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size));
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@@ -90,7 +95,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() /
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gr_pd_ab_dist_cfg1_max_output_granularity_v();
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gk20a_writel(g, gr_pd_ab_dist_cfg1_r(),
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nvgpu_writel(g, gr_pd_ab_dist_cfg1_r(),
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gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
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gr_pd_ab_dist_cfg1_max_batches_init_f());
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@@ -103,15 +108,26 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
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ppc_index < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_index);
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ppc_index++) {
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val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
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stride + ppc_in_gpc_stride * ppc_index);
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val = nvgpu_readl(g, nvgpu_safe_add_u32(
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nvgpu_safe_add_u32(
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g->ops.gr.get_cbm_alpha_cb_size(),
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stride),
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nvgpu_safe_mult_u32(
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ppc_in_gpc_stride,
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ppc_index)));
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val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(),
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size *
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nvgpu_gr_config_get_pes_tpc_count(gr->config, gpc_index, ppc_index)));
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nvgpu_gr_config_get_pes_tpc_count(gr->config,
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gpc_index, ppc_index)));
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gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
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stride + ppc_in_gpc_stride * ppc_index, val);
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nvgpu_writel(g, nvgpu_safe_add_u32(
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nvgpu_safe_add_u32(
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g->ops.gr.get_cbm_alpha_cb_size(),
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stride),
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nvgpu_safe_mult_u32(
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ppc_in_gpc_stride,
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ppc_index)), val);
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}
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}
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}
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@@ -1,7 +1,7 @@
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/*
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* GV11B GPU GR
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*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -31,6 +31,7 @@ struct gk20a;
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struct nvgpu_warpstate;
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struct nvgpu_debug_context;
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u32 gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size(void);
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void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
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void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
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int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
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@@ -821,6 +821,7 @@ static const struct gops_gr ga100_ops_gr = {
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.gr_suspend = nvgpu_gr_suspend,
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#ifdef CONFIG_NVGPU_DEBUGGER
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.get_gr_status = gr_gm20b_get_gr_status,
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.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
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.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
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.set_circular_buffer_size = gr_ga100_set_circular_buffer_size,
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.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
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@@ -829,6 +829,7 @@ static const struct gops_gr ga10b_ops_gr = {
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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.get_gr_status = gr_gm20b_get_gr_status,
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.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
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.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
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.set_circular_buffer_size = gr_ga10b_set_circular_buffer_size,
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.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
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@@ -683,6 +683,7 @@ static const struct gops_gr gv11b_ops_gr = {
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#ifdef CONFIG_NVGPU_DEBUGGER
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.get_gr_status = gr_gm20b_get_gr_status,
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.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
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.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
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.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
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.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
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.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
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@@ -720,6 +720,7 @@ static const struct gops_gr tu104_ops_gr = {
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#ifdef CONFIG_NVGPU_DEBUGGER
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.get_gr_status = gr_gm20b_get_gr_status,
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.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size,
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.get_cbm_alpha_cb_size = gv11b_gr_gpc0_ppc0_cbm_alpha_cb_size,
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.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
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.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
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.get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,
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@@ -1245,6 +1245,7 @@ struct gops_gr {
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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#ifdef CONFIG_NVGPU_DEBUGGER
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u32 (*get_gr_status)(struct gk20a *g);
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u32 (*get_cbm_alpha_cb_size)(void);
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void (*set_alpha_circular_buffer_size)(struct gk20a *g,
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u32 data);
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void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
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