diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
index 36cc9b3ef..bbf5a1b68 100644
--- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
@@ -64,7 +64,7 @@ static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
 					   struct flcn_ucode_img *p_img);
 static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm);
 static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
-	struct nvgpu_mem *nonwpr);
+	struct nvgpu_mem *ucode);
 static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm);
 
 /*Globals*/
diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gp106.h b/drivers/gpu/nvgpu/common/pmu/acr_gp106.h
index 0fe3d1198..dcdb40ca0 100644
--- a/drivers/gpu/nvgpu/common/pmu/acr_gp106.h
+++ b/drivers/gpu/nvgpu/common/pmu/acr_gp106.h
@@ -59,7 +59,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
 int lsfm_discover_ucode_images(struct gk20a *g,
 	struct ls_flcn_mgr_v1 *plsfm);
 void lsfm_init_wpr_contents(struct gk20a *g,
-		struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *nonwpr);
+		struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode);
 int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
 	void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
 int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 669a775ff..5219f6705 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2004,7 +2004,7 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids,
 	}
 }
 
-void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
+void gk20a_fifo_recover(struct gk20a *g, u32 engine_ids,
 			u32 hw_id, bool id_is_tsg,
 			bool id_is_known, bool verbose, u32 rc_type)
 {
@@ -2024,7 +2024,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
 		id_type = ID_TYPE_UNKNOWN;
 	}
 
-	g->ops.fifo.teardown_ch_tsg(g, __engine_ids, hw_id, id_type,
+	g->ops.fifo.teardown_ch_tsg(g, engine_ids, hw_id, id_type,
 					 rc_type, NULL);
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 986dae738..ab9531cb0 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -274,7 +274,7 @@ int gk20a_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next);
 int nvgpu_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next,
 		bool wait_preempt);
 
-int gk20a_fifo_update_runlist(struct gk20a *g, u32 engine_id, u32 chid,
+int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 chid,
 			      bool add, bool wait_for_finish);
 
 int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
@@ -287,7 +287,7 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g);
 void gk20a_fifo_recover(struct gk20a *g,
 			u32 engine_ids, /* if zero, will be queried from HW */
 			u32 hw_id, /* if ~0, will be queried from HW */
-			bool hw_id_is_tsg, /* ignored if hw_id == ~0 */
+			bool id_is_tsg, /* ignored if hw_id == ~0 */
 			bool id_is_known, bool verbose, u32 rc_type);
 void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose,
 				u32 rc_type);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 1c937d1e4..afb23de70 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -598,16 +598,16 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
 				  u32 mode);
 
 struct nvgpu_gr_ctx;
-void gr_gk20a_ctx_patch_write(struct gk20a *g, struct nvgpu_gr_ctx *ch_ctx,
+void gr_gk20a_ctx_patch_write(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
 				    u32 addr, u32 data, bool patch);
 int gr_gk20a_ctx_patch_write_begin(struct gk20a *g,
-					  struct nvgpu_gr_ctx *ch_ctx,
+					  struct nvgpu_gr_ctx *gr_ctx,
 					  bool update_patch_count);
 void gr_gk20a_ctx_patch_write_end(struct gk20a *g,
-					struct nvgpu_gr_ctx *ch_ctx,
+					struct nvgpu_gr_ctx *gr_ctx,
 					bool update_patch_count);
 void gr_gk20a_commit_global_pagepool(struct gk20a *g,
-				     struct nvgpu_gr_ctx *ch_ctx,
+				     struct nvgpu_gr_ctx *gr_ctx,
 				     u64 addr, u32 size, bool patch);
 void gk20a_gr_set_shader_exceptions(struct gk20a *g, u32 data);
 void gr_gk20a_enable_hww_exceptions(struct gk20a *g);
@@ -622,7 +622,7 @@ void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base,
 	struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
 
 
-void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c);
+void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *tsg);
 int gr_gk20a_disable_ctxsw(struct gk20a *g);
 int gr_gk20a_enable_ctxsw(struct gk20a *g);
 void gk20a_gr_resume_single_sm(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 76a162162..a9daaa2e5 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -142,7 +142,7 @@ u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
 
 const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
 						      u32 big_page_size);
-void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,
+void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
 		struct vm_gk20a *vm);
 
 extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.h b/drivers/gpu/nvgpu/gp106/hal_gp106.h
index d46dacec1..856acf537 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.h
@@ -26,5 +26,5 @@
 #define NVGPU_HAL_GP106_H
 struct gk20a;
 
-int gp106_init_hal(struct gk20a *gops);
+int gp106_init_hal(struct gk20a *g);
 #endif /* NVGPU_HAL_GP106_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 2ae44e04e..0cde1f32a 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -79,7 +79,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
 			struct channel_gk20a *c, bool patch);
 void gr_gp10b_commit_global_pagepool(struct gk20a *g,
-					    struct nvgpu_gr_ctx *ch_ctx,
+					    struct nvgpu_gr_ctx *gr_ctx,
 					    u64 addr, u32 size, bool patch);
 u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
 u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
@@ -116,10 +116,10 @@ void gr_gp10b_dump_ctxsw_stats(struct gk20a *g, struct vm_gk20a *vm,
 int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
 			       u32 expect_delay);
 void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
-					     struct nvgpu_gr_ctx *ch_ctx,
+					     struct nvgpu_gr_ctx *gr_ctx,
 					     u64 addr, bool patch);
 void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
-					    struct nvgpu_gr_ctx *ch_ctx,
+					    struct nvgpu_gr_ctx *gr_ctx,
 					    u64 addr, u64 size, bool patch);
 int gr_gp10b_load_smid_config(struct gk20a *g);
 void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
index 13103c178..0bf3d00da 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
@@ -26,6 +26,6 @@
 #define NVGPU_HAL_GP10B_H
 struct gk20a;
 
-int gp10b_init_hal(struct gk20a *gops);
+int gp10b_init_hal(struct gk20a *g);
 u32 gp10b_get_litter_value(struct gk20a *g, int value);
 #endif /* NVGPU_HAL_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h
index a4b295419..f00c4c03f 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h
@@ -27,6 +27,6 @@
 
 struct gk20a;
 
-int gv100_init_hal(struct gk20a *gops);
+int gv100_init_hal(struct gk20a *g);
 
 #endif /* NVGPU_HAL_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 722287159..84786c293 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -133,7 +133,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
 		       u32 expect_delay);
 void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
-					     struct nvgpu_gr_ctx *ch_ctx,
+					     struct nvgpu_gr_ctx *gr_ctx,
 					     u64 addr, bool patch);
 void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
 void gr_gv11b_get_access_map(struct gk20a *g,
@@ -219,7 +219,8 @@ int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr,
 	enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num,
 	u32 *broadcast_flags);
 void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
-	 u32 gpc, u32 tpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t);
+				u32 gpc_num, u32 tpc_num, u32 broadcast_flags,
+				u32 *priv_addr_table, u32 *t);
 u32 gv11b_gr_get_egpc_base(struct gk20a *g);
 void gr_gv11b_init_gpc_mmu(struct gk20a *g);
 int gr_gv11b_init_preemption_state(struct gk20a *g);
@@ -234,8 +235,8 @@ int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g,
                                 u32 compute_preempt_mode);
 
 void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
-                struct channel_gk20a *ch_ctx,
-                struct nvgpu_mem *mem);
+		struct channel_gk20a *c,
+		struct nvgpu_mem *mem);
 int gr_gv11b_handle_ssync_hww(struct gk20a *g);
 u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm);
 
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
index b10cc7270..7b75c9723 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h
@@ -26,6 +26,6 @@
 #define NVGPU_HAL_GV11B_H
 struct gk20a;
 
-int gv11b_init_hal(struct gk20a *gops);
+int gv11b_init_hal(struct gk20a *g);
 u32 gv11b_get_litter_value(struct gk20a *g, int value);
 #endif /* NVGPU_HAL_GV11B_H */
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.h b/drivers/gpu/nvgpu/tu104/hal_tu104.h
index 36f36d302..28ffdd463 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.h
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.h
@@ -27,6 +27,6 @@
 
 struct gk20a;
 
-int tu104_init_hal(struct gk20a *gops);
+int tu104_init_hal(struct gk20a *g);
 
 #endif /* NVGPU_HAL_TU104_H */